1 /*
2  * SH7264 Setup
3  *
4  * Copyright (C) 2012  Renesas Electronics Europe Ltd
5  *
6  * This file is subject to the terms and conditions of the GNU General Public
7  * License.  See the file "COPYING" in the main directory of this archive
8  * for more details.
9  */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/usb/r8a66597.h>
15 #include <linux/sh_timer.h>
16 #include <linux/io.h>
17 
18 enum {
19 	UNUSED = 0,
20 
21 	/* interrupt sources */
22 	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
23 	PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
24 
25 	DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
26 	DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
27 	USB, VDC3, CMT0, CMT1, BSC, WDT,
28 	MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
29 	MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
30 	PWMT1, PWMT2, ADC_ADI,
31 	SSIF0, SSII1, SSII2, SSII3,
32 	RSPDIF,
33 	IIC30, IIC31, IIC32, IIC33,
34 	SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
35 	SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
36 	SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
37 	SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
38 	SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
39 	SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
40 	SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
41 	SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
42 	SIO_FIFO, RSPIC0, RSPIC1,
43 	RCAN0, RCAN1, IEBC, CD_ROMD,
44 	NFMC, SDHI, RTC,
45 	SRCC0, SRCC1, DCOMU, OFFI, IFEI,
46 
47 	/* interrupt groups */
48 	PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
49 };
50 
51 static struct intc_vect vectors[] __initdata = {
52 	INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
53 	INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
54 	INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
55 	INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
56 
57 	INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
58 	INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
59 	INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
60 	INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
61 
62 	INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
63 	INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
64 	INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
65 	INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
66 	INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
67 	INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
68 	INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
69 	INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
70 	INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
71 	INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
72 	INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
73 	INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
74 	INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
75 	INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
76 	INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
77 	INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
78 
79 	INTC_IRQ(USB, 170),
80 	INTC_IRQ(VDC3, 171), INTC_IRQ(VDC3, 172),
81 	INTC_IRQ(VDC3, 173), INTC_IRQ(VDC3, 174),
82 	INTC_IRQ(CMT0, 175), INTC_IRQ(CMT1, 176),
83 	INTC_IRQ(BSC, 177), INTC_IRQ(WDT, 178),
84 
85 	INTC_IRQ(MTU0_ABCD, 179), INTC_IRQ(MTU0_ABCD, 180),
86 	INTC_IRQ(MTU0_ABCD, 181), INTC_IRQ(MTU0_ABCD, 182),
87 	INTC_IRQ(MTU0_VEF, 183),
88 	INTC_IRQ(MTU0_VEF, 184), INTC_IRQ(MTU0_VEF, 185),
89 	INTC_IRQ(MTU1_AB, 186), INTC_IRQ(MTU1_AB, 187),
90 	INTC_IRQ(MTU1_VU, 188), INTC_IRQ(MTU1_VU, 189),
91 	INTC_IRQ(MTU2_AB, 190), INTC_IRQ(MTU2_AB, 191),
92 	INTC_IRQ(MTU2_VU, 192), INTC_IRQ(MTU2_VU, 193),
93 	INTC_IRQ(MTU3_ABCD, 194), INTC_IRQ(MTU3_ABCD, 195),
94 	INTC_IRQ(MTU3_ABCD, 196), INTC_IRQ(MTU3_ABCD, 197),
95 	INTC_IRQ(MTU3_TCI3V, 198),
96 	INTC_IRQ(MTU4_ABCD, 199), INTC_IRQ(MTU4_ABCD, 200),
97 	INTC_IRQ(MTU4_ABCD, 201), INTC_IRQ(MTU4_ABCD, 202),
98 	INTC_IRQ(MTU4_TCI4V, 203),
99 
100 	INTC_IRQ(PWMT1, 204), INTC_IRQ(PWMT2, 205),
101 
102 	INTC_IRQ(ADC_ADI, 206),
103 
104 	INTC_IRQ(SSIF0, 207), INTC_IRQ(SSIF0, 208),
105 	INTC_IRQ(SSIF0, 209),
106 	INTC_IRQ(SSII1, 210), INTC_IRQ(SSII1, 211),
107 	INTC_IRQ(SSII2, 212), INTC_IRQ(SSII2, 213),
108 	INTC_IRQ(SSII3, 214), INTC_IRQ(SSII3, 215),
109 
110 	INTC_IRQ(RSPDIF, 216),
111 
112 	INTC_IRQ(IIC30, 217), INTC_IRQ(IIC30, 218),
113 	INTC_IRQ(IIC30, 219), INTC_IRQ(IIC30, 220),
114 	INTC_IRQ(IIC30, 221),
115 	INTC_IRQ(IIC31, 222), INTC_IRQ(IIC31, 223),
116 	INTC_IRQ(IIC31, 224), INTC_IRQ(IIC31, 225),
117 	INTC_IRQ(IIC31, 226),
118 	INTC_IRQ(IIC32, 227), INTC_IRQ(IIC32, 228),
119 	INTC_IRQ(IIC32, 229), INTC_IRQ(IIC32, 230),
120 	INTC_IRQ(IIC32, 231),
121 
122 	INTC_IRQ(SCIF0_BRI, 232), INTC_IRQ(SCIF0_ERI, 233),
123 	INTC_IRQ(SCIF0_RXI, 234), INTC_IRQ(SCIF0_TXI, 235),
124 	INTC_IRQ(SCIF1_BRI, 236), INTC_IRQ(SCIF1_ERI, 237),
125 	INTC_IRQ(SCIF1_RXI, 238), INTC_IRQ(SCIF1_TXI, 239),
126 	INTC_IRQ(SCIF2_BRI, 240), INTC_IRQ(SCIF2_ERI, 241),
127 	INTC_IRQ(SCIF2_RXI, 242), INTC_IRQ(SCIF2_TXI, 243),
128 	INTC_IRQ(SCIF3_BRI, 244), INTC_IRQ(SCIF3_ERI, 245),
129 	INTC_IRQ(SCIF3_RXI, 246), INTC_IRQ(SCIF3_TXI, 247),
130 	INTC_IRQ(SCIF4_BRI, 248), INTC_IRQ(SCIF4_ERI, 249),
131 	INTC_IRQ(SCIF4_RXI, 250), INTC_IRQ(SCIF4_TXI, 251),
132 	INTC_IRQ(SCIF5_BRI, 252), INTC_IRQ(SCIF5_ERI, 253),
133 	INTC_IRQ(SCIF5_RXI, 254), INTC_IRQ(SCIF5_TXI, 255),
134 	INTC_IRQ(SCIF6_BRI, 256), INTC_IRQ(SCIF6_ERI, 257),
135 	INTC_IRQ(SCIF6_RXI, 258), INTC_IRQ(SCIF6_TXI, 259),
136 	INTC_IRQ(SCIF7_BRI, 260), INTC_IRQ(SCIF7_ERI, 261),
137 	INTC_IRQ(SCIF7_RXI, 262), INTC_IRQ(SCIF7_TXI, 263),
138 
139 	INTC_IRQ(SIO_FIFO, 264),
140 
141 	INTC_IRQ(RSPIC0, 265), INTC_IRQ(RSPIC0, 266),
142 	INTC_IRQ(RSPIC0, 267),
143 	INTC_IRQ(RSPIC1, 268), INTC_IRQ(RSPIC1, 269),
144 	INTC_IRQ(RSPIC1, 270),
145 
146 	INTC_IRQ(RCAN0, 271), INTC_IRQ(RCAN0, 272),
147 	INTC_IRQ(RCAN0, 273), INTC_IRQ(RCAN0, 274),
148 	INTC_IRQ(RCAN0, 275),
149 	INTC_IRQ(RCAN1, 276), INTC_IRQ(RCAN1, 277),
150 	INTC_IRQ(RCAN1, 278), INTC_IRQ(RCAN1, 279),
151 	INTC_IRQ(RCAN1, 280),
152 
153 	INTC_IRQ(IEBC, 281),
154 
155 	INTC_IRQ(CD_ROMD, 282), INTC_IRQ(CD_ROMD, 283),
156 	INTC_IRQ(CD_ROMD, 284), INTC_IRQ(CD_ROMD, 285),
157 	INTC_IRQ(CD_ROMD, 286), INTC_IRQ(CD_ROMD, 287),
158 
159 	INTC_IRQ(NFMC, 288), INTC_IRQ(NFMC, 289),
160 	INTC_IRQ(NFMC, 290), INTC_IRQ(NFMC, 291),
161 
162 	INTC_IRQ(SDHI, 292), INTC_IRQ(SDHI, 293),
163 	INTC_IRQ(SDHI, 294),
164 
165 	INTC_IRQ(RTC, 296), INTC_IRQ(RTC, 297),
166 	INTC_IRQ(RTC, 298),
167 
168 	INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300),
169 	INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302),
170 	INTC_IRQ(SRCC0, 303),
171 	INTC_IRQ(SRCC1, 304), INTC_IRQ(SRCC1, 305),
172 	INTC_IRQ(SRCC1, 306), INTC_IRQ(SRCC1, 307),
173 	INTC_IRQ(SRCC1, 308),
174 
175 	INTC_IRQ(DCOMU, 310), INTC_IRQ(DCOMU, 311),
176 	INTC_IRQ(DCOMU, 312),
177 };
178 
179 static struct intc_group groups[] __initdata = {
180 	INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
181 		   PINT4, PINT5, PINT6, PINT7),
182 	INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
183 	INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
184 	INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
185 	INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
186 	INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
187 	INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
188 	INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
189 	INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
190 };
191 
192 static struct intc_prio_reg prio_registers[] __initdata = {
193 	{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
194 	{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
195 	{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
196 	{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0,  DMAC1,  DMAC2,  DMAC3 } },
197 	{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4,  DMAC5,  DMAC6,  DMAC7 } },
198 	{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8,  DMAC9,
199 					      DMAC10, DMAC11 } },
200 	{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
201 					      DMAC14, DMAC15 } },
202 	{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC3, CMT0, CMT1 } },
203 	{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
204 	{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU1_AB, MTU1_VU,
205 					      MTU2_AB, MTU2_VU } },
206 	{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU3_ABCD, MTU3_TCI3V,
207 					      MTU4_ABCD, MTU4_TCI4V } },
208 	{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { PWMT1, PWMT2, ADC_ADI, 0 } },
209 	{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSIF0, SSII1, SSII2, SSII3 } },
210 	{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { RSPDIF, IIC30, IIC31, IIC32 } },
211 	{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
212 	{ 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
213 	{ 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { SIO_FIFO, 0, RSPIC0, RSPIC1, } },
214 	{ 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { RCAN0, RCAN1, IEBC, CD_ROMD } },
215 	{ 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { NFMC, SDHI, RTC, 0 } },
216 	{ 0xfffe0c20, 0, 16, 4, /* IPR22 */ { SRCC0, SRCC1, 0, DCOMU } },
217 };
218 
219 static struct intc_mask_reg mask_registers[] __initdata = {
220 	{ 0xfffe0808, 0, 16, /* PINTER */
221 	  { 0, 0, 0, 0, 0, 0, 0, 0,
222 	    PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
223 };
224 
225 static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
226 			 mask_registers, prio_registers, NULL);
227 
228 static struct plat_sci_port scif0_platform_data = {
229 	.mapbase	= 0xfffe8000,
230 	.flags		= UPF_BOOT_AUTOCONF,
231 	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
232 			  SCSCR_REIE | SCSCR_TOIE,
233 	.scbrr_algo_id	= SCBRR_ALGO_2,
234 	.type		= PORT_SCIF,
235 	.irqs		=  { 233, 234, 235, 232 },
236 	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
237 };
238 
239 static struct platform_device scif0_device = {
240 	.name		= "sh-sci",
241 	.id		= 0,
242 	.dev		= {
243 		.platform_data	= &scif0_platform_data,
244 	},
245 };
246 
247 static struct plat_sci_port scif1_platform_data = {
248 	.mapbase	= 0xfffe8800,
249 	.flags		= UPF_BOOT_AUTOCONF,
250 	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
251 			  SCSCR_REIE | SCSCR_TOIE,
252 	.scbrr_algo_id	= SCBRR_ALGO_2,
253 	.type		= PORT_SCIF,
254 	.irqs		=  { 237, 238, 239, 236 },
255 	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
256 };
257 
258 static struct platform_device scif1_device = {
259 	.name		= "sh-sci",
260 	.id		= 1,
261 	.dev		= {
262 		.platform_data	= &scif1_platform_data,
263 	},
264 };
265 
266 static struct plat_sci_port scif2_platform_data = {
267 	.mapbase	= 0xfffe9000,
268 	.flags		= UPF_BOOT_AUTOCONF,
269 	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
270 			  SCSCR_REIE | SCSCR_TOIE,
271 	.scbrr_algo_id	= SCBRR_ALGO_2,
272 	.type		= PORT_SCIF,
273 	.irqs		=  { 241, 242, 243, 240 },
274 	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
275 };
276 
277 static struct platform_device scif2_device = {
278 	.name		= "sh-sci",
279 	.id		= 2,
280 	.dev		= {
281 		.platform_data	= &scif2_platform_data,
282 	},
283 };
284 
285 static struct plat_sci_port scif3_platform_data = {
286 	.mapbase	= 0xfffe9800,
287 	.flags		= UPF_BOOT_AUTOCONF,
288 	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
289 			  SCSCR_REIE | SCSCR_TOIE,
290 	.scbrr_algo_id	= SCBRR_ALGO_2,
291 	.type		= PORT_SCIF,
292 	.irqs		=  { 245, 246, 247, 244 },
293 	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
294 };
295 
296 static struct platform_device scif3_device = {
297 	.name		= "sh-sci",
298 	.id		= 3,
299 	.dev		= {
300 		.platform_data	= &scif3_platform_data,
301 	},
302 };
303 
304 static struct plat_sci_port scif4_platform_data = {
305 	.mapbase	= 0xfffea000,
306 	.flags		= UPF_BOOT_AUTOCONF,
307 	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
308 			  SCSCR_REIE | SCSCR_TOIE,
309 	.scbrr_algo_id	= SCBRR_ALGO_2,
310 	.type		= PORT_SCIF,
311 	.irqs		=  { 249, 250, 251, 248 },
312 	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
313 };
314 
315 static struct platform_device scif4_device = {
316 	.name		= "sh-sci",
317 	.id		= 4,
318 	.dev		= {
319 		.platform_data	= &scif4_platform_data,
320 	},
321 };
322 
323 static struct plat_sci_port scif5_platform_data = {
324 	.mapbase	= 0xfffea800,
325 	.flags		= UPF_BOOT_AUTOCONF,
326 	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
327 			  SCSCR_REIE | SCSCR_TOIE,
328 	.scbrr_algo_id	= SCBRR_ALGO_2,
329 	.type		= PORT_SCIF,
330 	.irqs		=  { 253, 254, 255, 252 },
331 	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
332 };
333 
334 static struct platform_device scif5_device = {
335 	.name		= "sh-sci",
336 	.id		= 5,
337 	.dev		= {
338 		.platform_data	= &scif5_platform_data,
339 	},
340 };
341 
342 static struct plat_sci_port scif6_platform_data = {
343 	.mapbase	= 0xfffeb000,
344 	.flags		= UPF_BOOT_AUTOCONF,
345 	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
346 			  SCSCR_REIE | SCSCR_TOIE,
347 	.scbrr_algo_id	= SCBRR_ALGO_2,
348 	.type		= PORT_SCIF,
349 	.irqs		=  { 257, 258, 259, 256 },
350 	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
351 };
352 
353 static struct platform_device scif6_device = {
354 	.name		= "sh-sci",
355 	.id		= 6,
356 	.dev		= {
357 		.platform_data	= &scif6_platform_data,
358 	},
359 };
360 
361 static struct plat_sci_port scif7_platform_data = {
362 	.mapbase	= 0xfffeb800,
363 	.flags		= UPF_BOOT_AUTOCONF,
364 	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
365 			  SCSCR_REIE | SCSCR_TOIE,
366 	.scbrr_algo_id	= SCBRR_ALGO_2,
367 	.type		= PORT_SCIF,
368 	.irqs		=  { 261, 262, 263, 260 },
369 	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
370 };
371 
372 static struct platform_device scif7_device = {
373 	.name		= "sh-sci",
374 	.id		= 7,
375 	.dev		= {
376 		.platform_data	= &scif7_platform_data,
377 	},
378 };
379 
380 static struct sh_timer_config cmt0_platform_data = {
381 	.channel_offset = 0x02,
382 	.timer_bit = 0,
383 	.clockevent_rating = 125,
384 	.clocksource_rating = 0, /* disabled due to code generation issues */
385 };
386 
387 static struct resource cmt0_resources[] = {
388 	[0] = {
389 		.name	= "CMT0",
390 		.start	= 0xfffec002,
391 		.end	= 0xfffec007,
392 		.flags	= IORESOURCE_MEM,
393 	},
394 	[1] = {
395 		.start	= 175,
396 		.flags	= IORESOURCE_IRQ,
397 	},
398 };
399 
400 static struct platform_device cmt0_device = {
401 	.name		= "sh_cmt",
402 	.id		= 0,
403 	.dev = {
404 		.platform_data	= &cmt0_platform_data,
405 	},
406 	.resource	= cmt0_resources,
407 	.num_resources	= ARRAY_SIZE(cmt0_resources),
408 };
409 
410 static struct sh_timer_config cmt1_platform_data = {
411 	.name = "CMT1",
412 	.channel_offset = 0x08,
413 	.timer_bit = 1,
414 	.clockevent_rating = 125,
415 	.clocksource_rating = 0, /* disabled due to code generation issues */
416 };
417 
418 static struct resource cmt1_resources[] = {
419 	[0] = {
420 		.name	= "CMT1",
421 		.start	= 0xfffec008,
422 		.end	= 0xfffec00d,
423 		.flags	= IORESOURCE_MEM,
424 	},
425 	[1] = {
426 		.start	= 176,
427 		.flags	= IORESOURCE_IRQ,
428 	},
429 };
430 
431 static struct platform_device cmt1_device = {
432 	.name		= "sh_cmt",
433 	.id		= 1,
434 	.dev = {
435 		.platform_data	= &cmt1_platform_data,
436 	},
437 	.resource	= cmt1_resources,
438 	.num_resources	= ARRAY_SIZE(cmt1_resources),
439 };
440 
441 static struct sh_timer_config mtu2_0_platform_data = {
442 	.name = "MTU2_0",
443 	.channel_offset = -0x80,
444 	.timer_bit = 0,
445 	.clockevent_rating = 200,
446 };
447 
448 static struct resource mtu2_0_resources[] = {
449 	[0] = {
450 		.name	= "MTU2_0",
451 		.start	= 0xfffe4300,
452 		.end	= 0xfffe4326,
453 		.flags	= IORESOURCE_MEM,
454 	},
455 	[1] = {
456 		.start	= 179,
457 		.flags	= IORESOURCE_IRQ,
458 	},
459 };
460 
461 static struct platform_device mtu2_0_device = {
462 	.name		= "sh_mtu2",
463 	.id		= 0,
464 	.dev = {
465 		.platform_data	= &mtu2_0_platform_data,
466 	},
467 	.resource	= mtu2_0_resources,
468 	.num_resources	= ARRAY_SIZE(mtu2_0_resources),
469 };
470 
471 static struct sh_timer_config mtu2_1_platform_data = {
472 	.name = "MTU2_1",
473 	.channel_offset = -0x100,
474 	.timer_bit = 1,
475 	.clockevent_rating = 200,
476 };
477 
478 static struct resource mtu2_1_resources[] = {
479 	[0] = {
480 		.name	= "MTU2_1",
481 		.start	= 0xfffe4380,
482 		.end	= 0xfffe4390,
483 		.flags	= IORESOURCE_MEM,
484 	},
485 	[1] = {
486 		.start	= 186,
487 		.flags	= IORESOURCE_IRQ,
488 	},
489 };
490 
491 static struct platform_device mtu2_1_device = {
492 	.name		= "sh_mtu2",
493 	.id		= 1,
494 	.dev = {
495 		.platform_data	= &mtu2_1_platform_data,
496 	},
497 	.resource	= mtu2_1_resources,
498 	.num_resources	= ARRAY_SIZE(mtu2_1_resources),
499 };
500 
501 static struct resource rtc_resources[] = {
502 	[0] = {
503 		.start	= 0xfffe6000,
504 		.end	= 0xfffe6000 + 0x30 - 1,
505 		.flags	= IORESOURCE_IO,
506 	},
507 	[1] = {
508 		/* Shared Period/Carry/Alarm IRQ */
509 		.start	= 296,
510 		.flags	= IORESOURCE_IRQ,
511 	},
512 };
513 
514 static struct platform_device rtc_device = {
515 	.name		= "sh-rtc",
516 	.id		= -1,
517 	.num_resources	= ARRAY_SIZE(rtc_resources),
518 	.resource	= rtc_resources,
519 };
520 
521 /* USB Host */
522 static void usb_port_power(int port, int power)
523 {
524 	__raw_writew(0x200 , 0xffffc0c2) ; /* Initialise UACS25 */
525 }
526 
527 static struct r8a66597_platdata r8a66597_data = {
528 	.on_chip = 1,
529 	.endian = 1,
530 	.port_power = usb_port_power,
531 };
532 
533 static struct resource r8a66597_usb_host_resources[] = {
534 	[0] = {
535 		.start	= 0xffffc000,
536 		.end	= 0xffffc0e4,
537 		.flags	= IORESOURCE_MEM,
538 	},
539 	[1] = {
540 		.start	= 170,
541 		.end	= 170,
542 		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
543 	},
544 };
545 
546 static struct platform_device r8a66597_usb_host_device = {
547 	.name		= "r8a66597_hcd",
548 	.id		= 0,
549 	.dev = {
550 		.dma_mask		= NULL,         /*  not use dma */
551 		.coherent_dma_mask	= 0xffffffff,
552 		.platform_data		= &r8a66597_data,
553 	},
554 	.num_resources	= ARRAY_SIZE(r8a66597_usb_host_resources),
555 	.resource	= r8a66597_usb_host_resources,
556 };
557 
558 static struct platform_device *sh7264_devices[] __initdata = {
559 	&scif0_device,
560 	&scif1_device,
561 	&scif2_device,
562 	&scif3_device,
563 	&scif4_device,
564 	&scif5_device,
565 	&scif6_device,
566 	&scif7_device,
567 	&cmt0_device,
568 	&cmt1_device,
569 	&mtu2_0_device,
570 	&mtu2_1_device,
571 	&rtc_device,
572 	&r8a66597_usb_host_device,
573 };
574 
575 static int __init sh7264_devices_setup(void)
576 {
577 	return platform_add_devices(sh7264_devices,
578 				    ARRAY_SIZE(sh7264_devices));
579 }
580 arch_initcall(sh7264_devices_setup);
581 
582 void __init plat_irq_setup(void)
583 {
584 	register_intc_controller(&intc_desc);
585 }
586 
587 static struct platform_device *sh7264_early_devices[] __initdata = {
588 	&scif0_device,
589 	&scif1_device,
590 	&scif2_device,
591 	&scif3_device,
592 	&scif4_device,
593 	&scif5_device,
594 	&scif6_device,
595 	&scif7_device,
596 	&cmt0_device,
597 	&cmt1_device,
598 	&mtu2_0_device,
599 	&mtu2_1_device,
600 };
601 
602 void __init plat_early_device_setup(void)
603 {
604 	early_platform_add_devices(sh7264_early_devices,
605 				   ARRAY_SIZE(sh7264_early_devices));
606 }
607