1 /* 2 * SH7264 Setup 3 * 4 * Copyright (C) 2012 Renesas Electronics Europe Ltd 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/serial_sci.h> 14 #include <linux/usb/r8a66597.h> 15 #include <linux/sh_timer.h> 16 #include <linux/io.h> 17 18 enum { 19 UNUSED = 0, 20 21 /* interrupt sources */ 22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 24 25 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, 26 DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15, 27 USB, VDC3, CMT0, CMT1, BSC, WDT, 28 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, 29 MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V, 30 PWMT1, PWMT2, ADC_ADI, 31 SSIF0, SSII1, SSII2, SSII3, 32 RSPDIF, 33 IIC30, IIC31, IIC32, IIC33, 34 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, 35 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI, 36 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI, 37 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI, 38 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI, 39 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI, 40 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI, 41 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI, 42 SIO_FIFO, RSPIC0, RSPIC1, 43 RCAN0, RCAN1, IEBC, CD_ROMD, 44 NFMC, SDHI, RTC, 45 SRCC0, SRCC1, DCOMU, OFFI, IFEI, 46 47 /* interrupt groups */ 48 PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7, 49 }; 50 51 static struct intc_vect vectors[] __initdata = { 52 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), 53 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 54 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), 55 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), 56 57 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), 58 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 59 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 60 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 61 62 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109), 63 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113), 64 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117), 65 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121), 66 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125), 67 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129), 68 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133), 69 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137), 70 INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141), 71 INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145), 72 INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149), 73 INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153), 74 INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157), 75 INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161), 76 INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165), 77 INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169), 78 79 INTC_IRQ(USB, 170), 80 INTC_IRQ(VDC3, 171), INTC_IRQ(VDC3, 172), 81 INTC_IRQ(VDC3, 173), INTC_IRQ(VDC3, 174), 82 INTC_IRQ(CMT0, 175), INTC_IRQ(CMT1, 176), 83 INTC_IRQ(BSC, 177), INTC_IRQ(WDT, 178), 84 85 INTC_IRQ(MTU0_ABCD, 179), INTC_IRQ(MTU0_ABCD, 180), 86 INTC_IRQ(MTU0_ABCD, 181), INTC_IRQ(MTU0_ABCD, 182), 87 INTC_IRQ(MTU0_VEF, 183), 88 INTC_IRQ(MTU0_VEF, 184), INTC_IRQ(MTU0_VEF, 185), 89 INTC_IRQ(MTU1_AB, 186), INTC_IRQ(MTU1_AB, 187), 90 INTC_IRQ(MTU1_VU, 188), INTC_IRQ(MTU1_VU, 189), 91 INTC_IRQ(MTU2_AB, 190), INTC_IRQ(MTU2_AB, 191), 92 INTC_IRQ(MTU2_VU, 192), INTC_IRQ(MTU2_VU, 193), 93 INTC_IRQ(MTU3_ABCD, 194), INTC_IRQ(MTU3_ABCD, 195), 94 INTC_IRQ(MTU3_ABCD, 196), INTC_IRQ(MTU3_ABCD, 197), 95 INTC_IRQ(MTU3_TCI3V, 198), 96 INTC_IRQ(MTU4_ABCD, 199), INTC_IRQ(MTU4_ABCD, 200), 97 INTC_IRQ(MTU4_ABCD, 201), INTC_IRQ(MTU4_ABCD, 202), 98 INTC_IRQ(MTU4_TCI4V, 203), 99 100 INTC_IRQ(PWMT1, 204), INTC_IRQ(PWMT2, 205), 101 102 INTC_IRQ(ADC_ADI, 206), 103 104 INTC_IRQ(SSIF0, 207), INTC_IRQ(SSIF0, 208), 105 INTC_IRQ(SSIF0, 209), 106 INTC_IRQ(SSII1, 210), INTC_IRQ(SSII1, 211), 107 INTC_IRQ(SSII2, 212), INTC_IRQ(SSII2, 213), 108 INTC_IRQ(SSII3, 214), INTC_IRQ(SSII3, 215), 109 110 INTC_IRQ(RSPDIF, 216), 111 112 INTC_IRQ(IIC30, 217), INTC_IRQ(IIC30, 218), 113 INTC_IRQ(IIC30, 219), INTC_IRQ(IIC30, 220), 114 INTC_IRQ(IIC30, 221), 115 INTC_IRQ(IIC31, 222), INTC_IRQ(IIC31, 223), 116 INTC_IRQ(IIC31, 224), INTC_IRQ(IIC31, 225), 117 INTC_IRQ(IIC31, 226), 118 INTC_IRQ(IIC32, 227), INTC_IRQ(IIC32, 228), 119 INTC_IRQ(IIC32, 229), INTC_IRQ(IIC32, 230), 120 INTC_IRQ(IIC32, 231), 121 122 INTC_IRQ(SCIF0_BRI, 232), INTC_IRQ(SCIF0_ERI, 233), 123 INTC_IRQ(SCIF0_RXI, 234), INTC_IRQ(SCIF0_TXI, 235), 124 INTC_IRQ(SCIF1_BRI, 236), INTC_IRQ(SCIF1_ERI, 237), 125 INTC_IRQ(SCIF1_RXI, 238), INTC_IRQ(SCIF1_TXI, 239), 126 INTC_IRQ(SCIF2_BRI, 240), INTC_IRQ(SCIF2_ERI, 241), 127 INTC_IRQ(SCIF2_RXI, 242), INTC_IRQ(SCIF2_TXI, 243), 128 INTC_IRQ(SCIF3_BRI, 244), INTC_IRQ(SCIF3_ERI, 245), 129 INTC_IRQ(SCIF3_RXI, 246), INTC_IRQ(SCIF3_TXI, 247), 130 INTC_IRQ(SCIF4_BRI, 248), INTC_IRQ(SCIF4_ERI, 249), 131 INTC_IRQ(SCIF4_RXI, 250), INTC_IRQ(SCIF4_TXI, 251), 132 INTC_IRQ(SCIF5_BRI, 252), INTC_IRQ(SCIF5_ERI, 253), 133 INTC_IRQ(SCIF5_RXI, 254), INTC_IRQ(SCIF5_TXI, 255), 134 INTC_IRQ(SCIF6_BRI, 256), INTC_IRQ(SCIF6_ERI, 257), 135 INTC_IRQ(SCIF6_RXI, 258), INTC_IRQ(SCIF6_TXI, 259), 136 INTC_IRQ(SCIF7_BRI, 260), INTC_IRQ(SCIF7_ERI, 261), 137 INTC_IRQ(SCIF7_RXI, 262), INTC_IRQ(SCIF7_TXI, 263), 138 139 INTC_IRQ(SIO_FIFO, 264), 140 141 INTC_IRQ(RSPIC0, 265), INTC_IRQ(RSPIC0, 266), 142 INTC_IRQ(RSPIC0, 267), 143 INTC_IRQ(RSPIC1, 268), INTC_IRQ(RSPIC1, 269), 144 INTC_IRQ(RSPIC1, 270), 145 146 INTC_IRQ(RCAN0, 271), INTC_IRQ(RCAN0, 272), 147 INTC_IRQ(RCAN0, 273), INTC_IRQ(RCAN0, 274), 148 INTC_IRQ(RCAN0, 275), 149 INTC_IRQ(RCAN1, 276), INTC_IRQ(RCAN1, 277), 150 INTC_IRQ(RCAN1, 278), INTC_IRQ(RCAN1, 279), 151 INTC_IRQ(RCAN1, 280), 152 153 INTC_IRQ(IEBC, 281), 154 155 INTC_IRQ(CD_ROMD, 282), INTC_IRQ(CD_ROMD, 283), 156 INTC_IRQ(CD_ROMD, 284), INTC_IRQ(CD_ROMD, 285), 157 INTC_IRQ(CD_ROMD, 286), INTC_IRQ(CD_ROMD, 287), 158 159 INTC_IRQ(NFMC, 288), INTC_IRQ(NFMC, 289), 160 INTC_IRQ(NFMC, 290), INTC_IRQ(NFMC, 291), 161 162 INTC_IRQ(SDHI, 292), INTC_IRQ(SDHI, 293), 163 INTC_IRQ(SDHI, 294), 164 165 INTC_IRQ(RTC, 296), INTC_IRQ(RTC, 297), 166 INTC_IRQ(RTC, 298), 167 168 INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300), 169 INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302), 170 INTC_IRQ(SRCC0, 303), 171 INTC_IRQ(SRCC1, 304), INTC_IRQ(SRCC1, 305), 172 INTC_IRQ(SRCC1, 306), INTC_IRQ(SRCC1, 307), 173 INTC_IRQ(SRCC1, 308), 174 175 INTC_IRQ(DCOMU, 310), INTC_IRQ(DCOMU, 311), 176 INTC_IRQ(DCOMU, 312), 177 }; 178 179 static struct intc_group groups[] __initdata = { 180 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 181 PINT4, PINT5, PINT6, PINT7), 182 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI), 183 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI), 184 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI), 185 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI), 186 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI), 187 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI), 188 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI), 189 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI), 190 }; 191 192 static struct intc_prio_reg prio_registers[] __initdata = { 193 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 194 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 195 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } }, 196 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } }, 197 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } }, 198 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9, 199 DMAC10, DMAC11 } }, 200 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13, 201 DMAC14, DMAC15 } }, 202 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC3, CMT0, CMT1 } }, 203 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } }, 204 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU1_AB, MTU1_VU, 205 MTU2_AB, MTU2_VU } }, 206 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU3_ABCD, MTU3_TCI3V, 207 MTU4_ABCD, MTU4_TCI4V } }, 208 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { PWMT1, PWMT2, ADC_ADI, 0 } }, 209 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSIF0, SSII1, SSII2, SSII3 } }, 210 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { RSPDIF, IIC30, IIC31, IIC32 } }, 211 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { SCIF0, SCIF1, SCIF2, SCIF3 } }, 212 { 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SCIF4, SCIF5, SCIF6, SCIF7 } }, 213 { 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { SIO_FIFO, 0, RSPIC0, RSPIC1, } }, 214 { 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { RCAN0, RCAN1, IEBC, CD_ROMD } }, 215 { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { NFMC, SDHI, RTC, 0 } }, 216 { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { SRCC0, SRCC1, 0, DCOMU } }, 217 }; 218 219 static struct intc_mask_reg mask_registers[] __initdata = { 220 { 0xfffe0808, 0, 16, /* PINTER */ 221 { 0, 0, 0, 0, 0, 0, 0, 0, 222 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, 223 }; 224 225 static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups, 226 mask_registers, prio_registers, NULL); 227 228 static struct plat_sci_port scif0_platform_data = { 229 .scscr = SCSCR_REIE, 230 .type = PORT_SCIF, 231 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 232 }; 233 234 static struct resource scif0_resources[] = { 235 DEFINE_RES_MEM(0xfffe8000, 0x100), 236 DEFINE_RES_IRQ(233), 237 DEFINE_RES_IRQ(234), 238 DEFINE_RES_IRQ(235), 239 DEFINE_RES_IRQ(232), 240 }; 241 242 static struct platform_device scif0_device = { 243 .name = "sh-sci", 244 .id = 0, 245 .resource = scif0_resources, 246 .num_resources = ARRAY_SIZE(scif0_resources), 247 .dev = { 248 .platform_data = &scif0_platform_data, 249 }, 250 }; 251 252 static struct plat_sci_port scif1_platform_data = { 253 .scscr = SCSCR_REIE, 254 .type = PORT_SCIF, 255 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 256 }; 257 258 static struct resource scif1_resources[] = { 259 DEFINE_RES_MEM(0xfffe8800, 0x100), 260 DEFINE_RES_IRQ(237), 261 DEFINE_RES_IRQ(238), 262 DEFINE_RES_IRQ(239), 263 DEFINE_RES_IRQ(236), 264 }; 265 266 static struct platform_device scif1_device = { 267 .name = "sh-sci", 268 .id = 1, 269 .resource = scif1_resources, 270 .num_resources = ARRAY_SIZE(scif1_resources), 271 .dev = { 272 .platform_data = &scif1_platform_data, 273 }, 274 }; 275 276 static struct plat_sci_port scif2_platform_data = { 277 .scscr = SCSCR_REIE, 278 .type = PORT_SCIF, 279 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 280 }; 281 282 static struct resource scif2_resources[] = { 283 DEFINE_RES_MEM(0xfffe9000, 0x100), 284 DEFINE_RES_IRQ(241), 285 DEFINE_RES_IRQ(242), 286 DEFINE_RES_IRQ(243), 287 DEFINE_RES_IRQ(240), 288 }; 289 290 static struct platform_device scif2_device = { 291 .name = "sh-sci", 292 .id = 2, 293 .resource = scif2_resources, 294 .num_resources = ARRAY_SIZE(scif2_resources), 295 .dev = { 296 .platform_data = &scif2_platform_data, 297 }, 298 }; 299 300 static struct plat_sci_port scif3_platform_data = { 301 .scscr = SCSCR_REIE, 302 .type = PORT_SCIF, 303 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 304 }; 305 306 static struct resource scif3_resources[] = { 307 DEFINE_RES_MEM(0xfffe9800, 0x100), 308 DEFINE_RES_IRQ(245), 309 DEFINE_RES_IRQ(246), 310 DEFINE_RES_IRQ(247), 311 DEFINE_RES_IRQ(244), 312 }; 313 314 static struct platform_device scif3_device = { 315 .name = "sh-sci", 316 .id = 3, 317 .resource = scif3_resources, 318 .num_resources = ARRAY_SIZE(scif3_resources), 319 .dev = { 320 .platform_data = &scif3_platform_data, 321 }, 322 }; 323 324 static struct plat_sci_port scif4_platform_data = { 325 .scscr = SCSCR_REIE, 326 .type = PORT_SCIF, 327 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 328 }; 329 330 static struct resource scif4_resources[] = { 331 DEFINE_RES_MEM(0xfffea000, 0x100), 332 DEFINE_RES_IRQ(249), 333 DEFINE_RES_IRQ(250), 334 DEFINE_RES_IRQ(251), 335 DEFINE_RES_IRQ(248), 336 }; 337 338 static struct platform_device scif4_device = { 339 .name = "sh-sci", 340 .id = 4, 341 .resource = scif4_resources, 342 .num_resources = ARRAY_SIZE(scif4_resources), 343 .dev = { 344 .platform_data = &scif4_platform_data, 345 }, 346 }; 347 348 static struct plat_sci_port scif5_platform_data = { 349 .scscr = SCSCR_REIE, 350 .type = PORT_SCIF, 351 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 352 }; 353 354 static struct resource scif5_resources[] = { 355 DEFINE_RES_MEM(0xfffea800, 0x100), 356 DEFINE_RES_IRQ(253), 357 DEFINE_RES_IRQ(254), 358 DEFINE_RES_IRQ(255), 359 DEFINE_RES_IRQ(252), 360 }; 361 362 static struct platform_device scif5_device = { 363 .name = "sh-sci", 364 .id = 5, 365 .resource = scif5_resources, 366 .num_resources = ARRAY_SIZE(scif5_resources), 367 .dev = { 368 .platform_data = &scif5_platform_data, 369 }, 370 }; 371 372 static struct plat_sci_port scif6_platform_data = { 373 .scscr = SCSCR_REIE, 374 .type = PORT_SCIF, 375 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 376 }; 377 378 static struct resource scif6_resources[] = { 379 DEFINE_RES_MEM(0xfffeb000, 0x100), 380 DEFINE_RES_IRQ(257), 381 DEFINE_RES_IRQ(258), 382 DEFINE_RES_IRQ(259), 383 DEFINE_RES_IRQ(256), 384 }; 385 386 static struct platform_device scif6_device = { 387 .name = "sh-sci", 388 .id = 6, 389 .resource = scif6_resources, 390 .num_resources = ARRAY_SIZE(scif6_resources), 391 .dev = { 392 .platform_data = &scif6_platform_data, 393 }, 394 }; 395 396 static struct plat_sci_port scif7_platform_data = { 397 .scscr = SCSCR_REIE, 398 .type = PORT_SCIF, 399 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 400 }; 401 402 static struct resource scif7_resources[] = { 403 DEFINE_RES_MEM(0xfffeb800, 0x100), 404 DEFINE_RES_IRQ(261), 405 DEFINE_RES_IRQ(262), 406 DEFINE_RES_IRQ(263), 407 DEFINE_RES_IRQ(260), 408 }; 409 410 static struct platform_device scif7_device = { 411 .name = "sh-sci", 412 .id = 7, 413 .resource = scif7_resources, 414 .num_resources = ARRAY_SIZE(scif7_resources), 415 .dev = { 416 .platform_data = &scif7_platform_data, 417 }, 418 }; 419 420 static struct sh_timer_config cmt_platform_data = { 421 .channels_mask = 3, 422 }; 423 424 static struct resource cmt_resources[] = { 425 DEFINE_RES_MEM(0xfffec000, 0x10), 426 DEFINE_RES_IRQ(175), 427 DEFINE_RES_IRQ(176), 428 }; 429 430 static struct platform_device cmt_device = { 431 .name = "sh-cmt-16", 432 .id = 0, 433 .dev = { 434 .platform_data = &cmt_platform_data, 435 }, 436 .resource = cmt_resources, 437 .num_resources = ARRAY_SIZE(cmt_resources), 438 }; 439 440 static struct resource mtu2_resources[] = { 441 DEFINE_RES_MEM(0xfffe4000, 0x400), 442 DEFINE_RES_IRQ_NAMED(179, "tgi0a"), 443 DEFINE_RES_IRQ_NAMED(186, "tgi1a"), 444 }; 445 446 static struct platform_device mtu2_device = { 447 .name = "sh-mtu2", 448 .id = -1, 449 .resource = mtu2_resources, 450 .num_resources = ARRAY_SIZE(mtu2_resources), 451 }; 452 453 static struct resource rtc_resources[] = { 454 [0] = { 455 .start = 0xfffe6000, 456 .end = 0xfffe6000 + 0x30 - 1, 457 .flags = IORESOURCE_IO, 458 }, 459 [1] = { 460 /* Shared Period/Carry/Alarm IRQ */ 461 .start = 296, 462 .flags = IORESOURCE_IRQ, 463 }, 464 }; 465 466 static struct platform_device rtc_device = { 467 .name = "sh-rtc", 468 .id = -1, 469 .num_resources = ARRAY_SIZE(rtc_resources), 470 .resource = rtc_resources, 471 }; 472 473 /* USB Host */ 474 static void usb_port_power(int port, int power) 475 { 476 __raw_writew(0x200 , 0xffffc0c2) ; /* Initialise UACS25 */ 477 } 478 479 static struct r8a66597_platdata r8a66597_data = { 480 .on_chip = 1, 481 .endian = 1, 482 .port_power = usb_port_power, 483 }; 484 485 static struct resource r8a66597_usb_host_resources[] = { 486 [0] = { 487 .start = 0xffffc000, 488 .end = 0xffffc0e4, 489 .flags = IORESOURCE_MEM, 490 }, 491 [1] = { 492 .start = 170, 493 .end = 170, 494 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 495 }, 496 }; 497 498 static struct platform_device r8a66597_usb_host_device = { 499 .name = "r8a66597_hcd", 500 .id = 0, 501 .dev = { 502 .dma_mask = NULL, /* not use dma */ 503 .coherent_dma_mask = 0xffffffff, 504 .platform_data = &r8a66597_data, 505 }, 506 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), 507 .resource = r8a66597_usb_host_resources, 508 }; 509 510 static struct platform_device *sh7264_devices[] __initdata = { 511 &scif0_device, 512 &scif1_device, 513 &scif2_device, 514 &scif3_device, 515 &scif4_device, 516 &scif5_device, 517 &scif6_device, 518 &scif7_device, 519 &cmt_device, 520 &mtu2_device, 521 &rtc_device, 522 &r8a66597_usb_host_device, 523 }; 524 525 static int __init sh7264_devices_setup(void) 526 { 527 return platform_add_devices(sh7264_devices, 528 ARRAY_SIZE(sh7264_devices)); 529 } 530 arch_initcall(sh7264_devices_setup); 531 532 void __init plat_irq_setup(void) 533 { 534 register_intc_controller(&intc_desc); 535 } 536 537 static struct platform_device *sh7264_early_devices[] __initdata = { 538 &scif0_device, 539 &scif1_device, 540 &scif2_device, 541 &scif3_device, 542 &scif4_device, 543 &scif5_device, 544 &scif6_device, 545 &scif7_device, 546 &cmt_device, 547 &mtu2_device, 548 }; 549 550 void __init plat_early_device_setup(void) 551 { 552 early_platform_add_devices(sh7264_early_devices, 553 ARRAY_SIZE(sh7264_early_devices)); 554 } 555