1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH7206 Setup 4 * 5 * Copyright (C) 2006 Yoshinori Sato 6 * Copyright (C) 2009 Paul Mundt 7 */ 8 #include <linux/platform_device.h> 9 #include <linux/init.h> 10 #include <linux/serial.h> 11 #include <linux/serial_sci.h> 12 #include <linux/sh_timer.h> 13 #include <linux/io.h> 14 15 enum { 16 UNUSED = 0, 17 18 /* interrupt sources */ 19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 21 ADC_ADI0, ADC_ADI1, 22 23 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, 24 25 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, 26 MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S, 27 IIC3, 28 29 CMT0, CMT1, BSC, WDT, 30 31 MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V, 32 33 POE2_OEI3, 34 35 SCIF0, SCIF1, SCIF2, SCIF3, 36 37 /* interrupt groups */ 38 PINT, 39 }; 40 41 static struct intc_vect vectors[] __initdata = { 42 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), 43 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 44 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), 45 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), 46 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), 47 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 48 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 49 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 50 INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96), 51 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109), 52 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113), 53 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117), 54 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121), 55 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125), 56 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129), 57 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133), 58 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137), 59 INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144), 60 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152), 61 INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157), 62 INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159), 63 INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161), 64 INTC_IRQ(MTU0_VEF, 162), 65 INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165), 66 INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169), 67 INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173), 68 INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177), 69 INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181), 70 INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183), 71 INTC_IRQ(MTU2_TCI3V, 184), 72 INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189), 73 INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191), 74 INTC_IRQ(MTU2_TCI4V, 192), 75 INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197), 76 INTC_IRQ(MTU5, 198), 77 INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201), 78 INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205), 79 INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207), 80 INTC_IRQ(MTU2S_TCI3V, 208), 81 INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213), 82 INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215), 83 INTC_IRQ(MTU2S_TCI4V, 216), 84 INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221), 85 INTC_IRQ(MTU5S, 222), 86 INTC_IRQ(POE2_OEI3, 224), 87 INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229), 88 INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231), 89 INTC_IRQ(IIC3, 232), 90 INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241), 91 INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243), 92 INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245), 93 INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247), 94 INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249), 95 INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251), 96 INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253), 97 INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255), 98 }; 99 100 static struct intc_group groups[] __initdata = { 101 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 102 PINT4, PINT5, PINT6, PINT7), 103 }; 104 105 static struct intc_prio_reg prio_registers[] __initdata = { 106 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 107 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 108 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } }, 109 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } }, 110 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } }, 111 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } }, 112 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF, 113 MTU1_AB, MTU1_VU } }, 114 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU, 115 MTU3_ABCD, MTU2_TCI3V } }, 116 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V, 117 MTU5, POE2_12 } }, 118 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V, 119 MTU4S_ABCD, MTU2S_TCI4V } }, 120 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } }, 121 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } }, 122 }; 123 124 static struct intc_mask_reg mask_registers[] __initdata = { 125 { 0xfffe0808, 0, 16, /* PINTER */ 126 { 0, 0, 0, 0, 0, 0, 0, 0, 127 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, 128 }; 129 130 static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups, 131 mask_registers, prio_registers, NULL); 132 133 static struct plat_sci_port scif0_platform_data = { 134 .scscr = SCSCR_REIE, 135 .type = PORT_SCIF, 136 }; 137 138 static struct resource scif0_resources[] = { 139 DEFINE_RES_MEM(0xfffe8000, 0x100), 140 DEFINE_RES_IRQ(240), 141 }; 142 143 static struct platform_device scif0_device = { 144 .name = "sh-sci", 145 .id = 0, 146 .resource = scif0_resources, 147 .num_resources = ARRAY_SIZE(scif0_resources), 148 .dev = { 149 .platform_data = &scif0_platform_data, 150 }, 151 }; 152 153 static struct plat_sci_port scif1_platform_data = { 154 .scscr = SCSCR_REIE, 155 .type = PORT_SCIF, 156 }; 157 158 static struct resource scif1_resources[] = { 159 DEFINE_RES_MEM(0xfffe8800, 0x100), 160 DEFINE_RES_IRQ(244), 161 }; 162 163 static struct platform_device scif1_device = { 164 .name = "sh-sci", 165 .id = 1, 166 .resource = scif1_resources, 167 .num_resources = ARRAY_SIZE(scif1_resources), 168 .dev = { 169 .platform_data = &scif1_platform_data, 170 }, 171 }; 172 173 static struct plat_sci_port scif2_platform_data = { 174 .scscr = SCSCR_REIE, 175 .type = PORT_SCIF, 176 }; 177 178 static struct resource scif2_resources[] = { 179 DEFINE_RES_MEM(0xfffe9000, 0x100), 180 DEFINE_RES_IRQ(248), 181 }; 182 183 static struct platform_device scif2_device = { 184 .name = "sh-sci", 185 .id = 2, 186 .resource = scif2_resources, 187 .num_resources = ARRAY_SIZE(scif2_resources), 188 .dev = { 189 .platform_data = &scif2_platform_data, 190 }, 191 }; 192 193 static struct plat_sci_port scif3_platform_data = { 194 .scscr = SCSCR_REIE, 195 .type = PORT_SCIF, 196 }; 197 198 static struct resource scif3_resources[] = { 199 DEFINE_RES_MEM(0xfffe9800, 0x100), 200 DEFINE_RES_IRQ(252), 201 }; 202 203 static struct platform_device scif3_device = { 204 .name = "sh-sci", 205 .id = 3, 206 .resource = scif3_resources, 207 .num_resources = ARRAY_SIZE(scif3_resources), 208 .dev = { 209 .platform_data = &scif3_platform_data, 210 }, 211 }; 212 213 static struct sh_timer_config cmt_platform_data = { 214 .channels_mask = 3, 215 }; 216 217 static struct resource cmt_resources[] = { 218 DEFINE_RES_MEM(0xfffec000, 0x10), 219 DEFINE_RES_IRQ(140), 220 DEFINE_RES_IRQ(144), 221 }; 222 223 static struct platform_device cmt_device = { 224 .name = "sh-cmt-16", 225 .id = 0, 226 .dev = { 227 .platform_data = &cmt_platform_data, 228 }, 229 .resource = cmt_resources, 230 .num_resources = ARRAY_SIZE(cmt_resources), 231 }; 232 233 static struct resource mtu2_resources[] = { 234 DEFINE_RES_MEM(0xfffe4000, 0x400), 235 DEFINE_RES_IRQ_NAMED(156, "tgi0a"), 236 DEFINE_RES_IRQ_NAMED(164, "tgi1a"), 237 DEFINE_RES_IRQ_NAMED(180, "tgi2a"), 238 }; 239 240 static struct platform_device mtu2_device = { 241 .name = "sh-mtu2s", 242 .id = -1, 243 .resource = mtu2_resources, 244 .num_resources = ARRAY_SIZE(mtu2_resources), 245 }; 246 247 static struct platform_device *sh7206_devices[] __initdata = { 248 &scif0_device, 249 &scif1_device, 250 &scif2_device, 251 &scif3_device, 252 &cmt_device, 253 &mtu2_device, 254 }; 255 256 static int __init sh7206_devices_setup(void) 257 { 258 return platform_add_devices(sh7206_devices, 259 ARRAY_SIZE(sh7206_devices)); 260 } 261 arch_initcall(sh7206_devices_setup); 262 263 void __init plat_irq_setup(void) 264 { 265 register_intc_controller(&intc_desc); 266 } 267 268 static struct platform_device *sh7206_early_devices[] __initdata = { 269 &scif0_device, 270 &scif1_device, 271 &scif2_device, 272 &scif3_device, 273 &cmt_device, 274 &mtu2_device, 275 }; 276 277 #define STBCR3 0xfffe0408 278 #define STBCR4 0xfffe040c 279 280 void __init plat_early_device_setup(void) 281 { 282 /* enable CMT clock */ 283 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4); 284 285 /* enable MTU2 clock */ 286 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3); 287 288 early_platform_add_devices(sh7206_early_devices, 289 ARRAY_SIZE(sh7206_early_devices)); 290 } 291