1 /* 2 * SH7206 Setup 3 * 4 * Copyright (C) 2006 Yoshinori Sato 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/serial.h> 14 #include <linux/serial_sci.h> 15 #include <linux/sh_timer.h> 16 #include <linux/io.h> 17 18 enum { 19 UNUSED = 0, 20 21 /* interrupt sources */ 22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 24 ADC_ADI0, ADC_ADI1, 25 26 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, 27 28 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, 29 MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S, 30 IIC3, 31 32 CMT0, CMT1, BSC, WDT, 33 34 MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V, 35 36 POE2_OEI3, 37 38 SCIF0, SCIF1, SCIF2, SCIF3, 39 40 /* interrupt groups */ 41 PINT, 42 }; 43 44 static struct intc_vect vectors[] __initdata = { 45 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), 46 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 47 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), 48 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), 49 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), 50 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 51 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 52 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 53 INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96), 54 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109), 55 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113), 56 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117), 57 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121), 58 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125), 59 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129), 60 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133), 61 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137), 62 INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144), 63 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152), 64 INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157), 65 INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159), 66 INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161), 67 INTC_IRQ(MTU0_VEF, 162), 68 INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165), 69 INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169), 70 INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173), 71 INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177), 72 INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181), 73 INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183), 74 INTC_IRQ(MTU2_TCI3V, 184), 75 INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189), 76 INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191), 77 INTC_IRQ(MTU2_TCI4V, 192), 78 INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197), 79 INTC_IRQ(MTU5, 198), 80 INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201), 81 INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205), 82 INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207), 83 INTC_IRQ(MTU2S_TCI3V, 208), 84 INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213), 85 INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215), 86 INTC_IRQ(MTU2S_TCI4V, 216), 87 INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221), 88 INTC_IRQ(MTU5S, 222), 89 INTC_IRQ(POE2_OEI3, 224), 90 INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229), 91 INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231), 92 INTC_IRQ(IIC3, 232), 93 INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241), 94 INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243), 95 INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245), 96 INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247), 97 INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249), 98 INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251), 99 INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253), 100 INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255), 101 }; 102 103 static struct intc_group groups[] __initdata = { 104 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 105 PINT4, PINT5, PINT6, PINT7), 106 }; 107 108 static struct intc_prio_reg prio_registers[] __initdata = { 109 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 110 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 111 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } }, 112 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } }, 113 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } }, 114 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } }, 115 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF, 116 MTU1_AB, MTU1_VU } }, 117 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU, 118 MTU3_ABCD, MTU2_TCI3V } }, 119 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V, 120 MTU5, POE2_12 } }, 121 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V, 122 MTU4S_ABCD, MTU2S_TCI4V } }, 123 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } }, 124 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } }, 125 }; 126 127 static struct intc_mask_reg mask_registers[] __initdata = { 128 { 0xfffe0808, 0, 16, /* PINTER */ 129 { 0, 0, 0, 0, 0, 0, 0, 0, 130 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, 131 }; 132 133 static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups, 134 mask_registers, prio_registers, NULL); 135 136 static struct plat_sci_port scif0_platform_data = { 137 .mapbase = 0xfffe8000, 138 .flags = UPF_BOOT_AUTOCONF, 139 .type = PORT_SCIF, 140 .irqs = { 240, 240, 240, 240 }, 141 }; 142 143 static struct platform_device scif0_device = { 144 .name = "sh-sci", 145 .id = 0, 146 .dev = { 147 .platform_data = &scif0_platform_data, 148 }, 149 }; 150 151 static struct plat_sci_port scif1_platform_data = { 152 .mapbase = 0xfffe8800, 153 .flags = UPF_BOOT_AUTOCONF, 154 .type = PORT_SCIF, 155 .irqs = { 244, 244, 244, 244 }, 156 }; 157 158 static struct platform_device scif1_device = { 159 .name = "sh-sci", 160 .id = 1, 161 .dev = { 162 .platform_data = &scif1_platform_data, 163 }, 164 }; 165 166 static struct plat_sci_port scif2_platform_data = { 167 .mapbase = 0xfffe9000, 168 .flags = UPF_BOOT_AUTOCONF, 169 .type = PORT_SCIF, 170 .irqs = { 248, 248, 248, 248 }, 171 }; 172 173 static struct platform_device scif2_device = { 174 .name = "sh-sci", 175 .id = 2, 176 .dev = { 177 .platform_data = &scif2_platform_data, 178 }, 179 }; 180 181 static struct plat_sci_port scif3_platform_data = { 182 .mapbase = 0xfffe9800, 183 .flags = UPF_BOOT_AUTOCONF, 184 .type = PORT_SCIF, 185 .irqs = { 252, 252, 252, 252 }, 186 }; 187 188 static struct platform_device scif3_device = { 189 .name = "sh-sci", 190 .id = 3, 191 .dev = { 192 .platform_data = &scif3_platform_data, 193 }, 194 }; 195 196 static struct sh_timer_config cmt0_platform_data = { 197 .name = "CMT0", 198 .channel_offset = 0x02, 199 .timer_bit = 0, 200 .clk = "peripheral_clk", 201 .clockevent_rating = 125, 202 .clocksource_rating = 0, /* disabled due to code generation issues */ 203 }; 204 205 static struct resource cmt0_resources[] = { 206 [0] = { 207 .name = "CMT0", 208 .start = 0xfffec002, 209 .end = 0xfffec007, 210 .flags = IORESOURCE_MEM, 211 }, 212 [1] = { 213 .start = 140, 214 .flags = IORESOURCE_IRQ, 215 }, 216 }; 217 218 static struct platform_device cmt0_device = { 219 .name = "sh_cmt", 220 .id = 0, 221 .dev = { 222 .platform_data = &cmt0_platform_data, 223 }, 224 .resource = cmt0_resources, 225 .num_resources = ARRAY_SIZE(cmt0_resources), 226 }; 227 228 static struct sh_timer_config cmt1_platform_data = { 229 .name = "CMT1", 230 .channel_offset = 0x08, 231 .timer_bit = 1, 232 .clk = "peripheral_clk", 233 .clockevent_rating = 125, 234 .clocksource_rating = 0, /* disabled due to code generation issues */ 235 }; 236 237 static struct resource cmt1_resources[] = { 238 [0] = { 239 .name = "CMT1", 240 .start = 0xfffec008, 241 .end = 0xfffec00d, 242 .flags = IORESOURCE_MEM, 243 }, 244 [1] = { 245 .start = 144, 246 .flags = IORESOURCE_IRQ, 247 }, 248 }; 249 250 static struct platform_device cmt1_device = { 251 .name = "sh_cmt", 252 .id = 1, 253 .dev = { 254 .platform_data = &cmt1_platform_data, 255 }, 256 .resource = cmt1_resources, 257 .num_resources = ARRAY_SIZE(cmt1_resources), 258 }; 259 260 static struct sh_timer_config mtu2_0_platform_data = { 261 .name = "MTU2_0", 262 .channel_offset = -0x80, 263 .timer_bit = 0, 264 .clk = "peripheral_clk", 265 .clockevent_rating = 200, 266 }; 267 268 static struct resource mtu2_0_resources[] = { 269 [0] = { 270 .name = "MTU2_0", 271 .start = 0xfffe4300, 272 .end = 0xfffe4326, 273 .flags = IORESOURCE_MEM, 274 }, 275 [1] = { 276 .start = 156, 277 .flags = IORESOURCE_IRQ, 278 }, 279 }; 280 281 static struct platform_device mtu2_0_device = { 282 .name = "sh_mtu2", 283 .id = 0, 284 .dev = { 285 .platform_data = &mtu2_0_platform_data, 286 }, 287 .resource = mtu2_0_resources, 288 .num_resources = ARRAY_SIZE(mtu2_0_resources), 289 }; 290 291 static struct sh_timer_config mtu2_1_platform_data = { 292 .name = "MTU2_1", 293 .channel_offset = -0x100, 294 .timer_bit = 1, 295 .clk = "peripheral_clk", 296 .clockevent_rating = 200, 297 }; 298 299 static struct resource mtu2_1_resources[] = { 300 [0] = { 301 .name = "MTU2_1", 302 .start = 0xfffe4380, 303 .end = 0xfffe4390, 304 .flags = IORESOURCE_MEM, 305 }, 306 [1] = { 307 .start = 164, 308 .flags = IORESOURCE_IRQ, 309 }, 310 }; 311 312 static struct platform_device mtu2_1_device = { 313 .name = "sh_mtu2", 314 .id = 1, 315 .dev = { 316 .platform_data = &mtu2_1_platform_data, 317 }, 318 .resource = mtu2_1_resources, 319 .num_resources = ARRAY_SIZE(mtu2_1_resources), 320 }; 321 322 static struct sh_timer_config mtu2_2_platform_data = { 323 .name = "MTU2_2", 324 .channel_offset = 0x80, 325 .timer_bit = 2, 326 .clk = "peripheral_clk", 327 .clockevent_rating = 200, 328 }; 329 330 static struct resource mtu2_2_resources[] = { 331 [0] = { 332 .name = "MTU2_2", 333 .start = 0xfffe4000, 334 .end = 0xfffe400a, 335 .flags = IORESOURCE_MEM, 336 }, 337 [1] = { 338 .start = 180, 339 .flags = IORESOURCE_IRQ, 340 }, 341 }; 342 343 static struct platform_device mtu2_2_device = { 344 .name = "sh_mtu2", 345 .id = 2, 346 .dev = { 347 .platform_data = &mtu2_2_platform_data, 348 }, 349 .resource = mtu2_2_resources, 350 .num_resources = ARRAY_SIZE(mtu2_2_resources), 351 }; 352 353 static struct platform_device *sh7206_devices[] __initdata = { 354 &scif0_device, 355 &scif1_device, 356 &scif2_device, 357 &scif3_device, 358 &cmt0_device, 359 &cmt1_device, 360 &mtu2_0_device, 361 &mtu2_1_device, 362 &mtu2_2_device, 363 }; 364 365 static int __init sh7206_devices_setup(void) 366 { 367 return platform_add_devices(sh7206_devices, 368 ARRAY_SIZE(sh7206_devices)); 369 } 370 arch_initcall(sh7206_devices_setup); 371 372 void __init plat_irq_setup(void) 373 { 374 register_intc_controller(&intc_desc); 375 } 376 377 static struct platform_device *sh7206_early_devices[] __initdata = { 378 &scif0_device, 379 &scif1_device, 380 &scif2_device, 381 &scif3_device, 382 &cmt0_device, 383 &cmt1_device, 384 &mtu2_0_device, 385 &mtu2_1_device, 386 &mtu2_2_device, 387 }; 388 389 #define STBCR3 0xfffe0408 390 #define STBCR4 0xfffe040c 391 392 void __init plat_early_device_setup(void) 393 { 394 /* enable CMT clock */ 395 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4); 396 397 /* enable MTU2 clock */ 398 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3); 399 400 early_platform_add_devices(sh7206_early_devices, 401 ARRAY_SIZE(sh7206_early_devices)); 402 } 403