1 /* 2 * SH7203 and SH7263 Setup 3 * 4 * Copyright (C) 2007 - 2009 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/serial_sci.h> 14 #include <linux/sh_timer.h> 15 #include <linux/io.h> 16 17 enum { 18 UNUSED = 0, 19 20 /* interrupt sources */ 21 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 22 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 23 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, 24 USB, LCDC, CMT0, CMT1, BSC, WDT, 25 26 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, 27 MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V, 28 29 ADC_ADI, 30 31 IIC30, IIC31, IIC32, IIC33, 32 SCIF0, SCIF1, SCIF2, SCIF3, 33 34 SSU0, SSU1, 35 36 SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII, 37 38 /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */ 39 ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1, 40 SRC, IEBI, 41 42 /* interrupt groups */ 43 PINT, 44 }; 45 46 static struct intc_vect vectors[] __initdata = { 47 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), 48 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 49 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), 50 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), 51 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), 52 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 53 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 54 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 55 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109), 56 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113), 57 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117), 58 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121), 59 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125), 60 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129), 61 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133), 62 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137), 63 INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141), 64 INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143), 65 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145), 66 INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147), 67 INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149), 68 INTC_IRQ(MTU0_VEF, 150), 69 INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152), 70 INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154), 71 INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156), 72 INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158), 73 INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160), 74 INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162), 75 INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164), 76 INTC_IRQ(MTU2_TCI3V, 165), 77 INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167), 78 INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169), 79 INTC_IRQ(MTU2_TCI4V, 170), 80 INTC_IRQ(ADC_ADI, 171), 81 INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173), 82 INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175), 83 INTC_IRQ(IIC30, 176), 84 INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178), 85 INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180), 86 INTC_IRQ(IIC31, 181), 87 INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183), 88 INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185), 89 INTC_IRQ(IIC32, 186), 90 INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188), 91 INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190), 92 INTC_IRQ(IIC33, 191), 93 INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193), 94 INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195), 95 INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197), 96 INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199), 97 INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201), 98 INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203), 99 INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205), 100 INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207), 101 INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209), 102 INTC_IRQ(SSU0, 210), 103 INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212), 104 INTC_IRQ(SSU1, 213), 105 INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215), 106 INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217), 107 INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225), 108 INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227), 109 INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232), 110 INTC_IRQ(RTC, 233), 111 INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235), 112 INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237), 113 INTC_IRQ(RCAN0, 238), 114 INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240), 115 INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242), 116 INTC_IRQ(RCAN1, 243), 117 118 /* SH7263-specific trash */ 119 #ifdef CONFIG_CPU_SUBTYPE_SH7263 120 INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219), 121 INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221), 122 INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223), 123 124 INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229), 125 INTC_IRQ(SDHI, 230), 126 127 INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245), 128 INTC_IRQ(SRC, 246), 129 130 INTC_IRQ(IEBI, 247), 131 #endif 132 }; 133 134 static struct intc_group groups[] __initdata = { 135 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 136 PINT4, PINT5, PINT6, PINT7), 137 }; 138 139 static struct intc_prio_reg prio_registers[] __initdata = { 140 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 141 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 142 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } }, 143 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } }, 144 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } }, 145 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } }, 146 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } }, 147 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB, 148 MTU2_VU } }, 149 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD, 150 MTU2_TCI4V } }, 151 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } }, 152 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } }, 153 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } }, 154 #ifdef CONFIG_CPU_SUBTYPE_SH7203 155 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII, 156 SSI3_SSII, 0 } }, 157 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } }, 158 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } }, 159 #else 160 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII, 161 SSI3_SSII, ROMDEC } }, 162 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } }, 163 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } }, 164 #endif 165 }; 166 167 static struct intc_mask_reg mask_registers[] __initdata = { 168 { 0xfffe0808, 0, 16, /* PINTER */ 169 { 0, 0, 0, 0, 0, 0, 0, 0, 170 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, 171 }; 172 173 static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups, 174 mask_registers, prio_registers, NULL); 175 176 static struct plat_sci_port scif0_platform_data = { 177 .scscr = SCSCR_REIE, 178 .type = PORT_SCIF, 179 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 180 }; 181 182 static struct resource scif0_resources[] = { 183 DEFINE_RES_MEM(0xfffe8000, 0x100), 184 DEFINE_RES_IRQ(192), 185 }; 186 187 static struct platform_device scif0_device = { 188 .name = "sh-sci", 189 .id = 0, 190 .resource = scif0_resources, 191 .num_resources = ARRAY_SIZE(scif0_resources), 192 .dev = { 193 .platform_data = &scif0_platform_data, 194 }, 195 }; 196 197 static struct plat_sci_port scif1_platform_data = { 198 .scscr = SCSCR_REIE, 199 .type = PORT_SCIF, 200 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 201 }; 202 203 static struct resource scif1_resources[] = { 204 DEFINE_RES_MEM(0xfffe8800, 0x100), 205 DEFINE_RES_IRQ(196), 206 }; 207 208 static struct platform_device scif1_device = { 209 .name = "sh-sci", 210 .id = 1, 211 .resource = scif1_resources, 212 .num_resources = ARRAY_SIZE(scif1_resources), 213 .dev = { 214 .platform_data = &scif1_platform_data, 215 }, 216 }; 217 218 static struct plat_sci_port scif2_platform_data = { 219 .scscr = SCSCR_REIE, 220 .type = PORT_SCIF, 221 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 222 }; 223 224 static struct resource scif2_resources[] = { 225 DEFINE_RES_MEM(0xfffe9000, 0x100), 226 DEFINE_RES_IRQ(200), 227 }; 228 229 static struct platform_device scif2_device = { 230 .name = "sh-sci", 231 .id = 2, 232 .resource = scif2_resources, 233 .num_resources = ARRAY_SIZE(scif2_resources), 234 .dev = { 235 .platform_data = &scif2_platform_data, 236 }, 237 }; 238 239 static struct plat_sci_port scif3_platform_data = { 240 .scscr = SCSCR_REIE, 241 .type = PORT_SCIF, 242 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 243 }; 244 245 static struct resource scif3_resources[] = { 246 DEFINE_RES_MEM(0xfffe9800, 0x100), 247 DEFINE_RES_IRQ(204), 248 }; 249 250 static struct platform_device scif3_device = { 251 .name = "sh-sci", 252 .id = 3, 253 .resource = scif3_resources, 254 .num_resources = ARRAY_SIZE(scif3_resources), 255 .dev = { 256 .platform_data = &scif3_platform_data, 257 }, 258 }; 259 260 static struct sh_timer_config cmt_platform_data = { 261 .channels_mask = 3, 262 }; 263 264 static struct resource cmt_resources[] = { 265 DEFINE_RES_MEM(0xfffec000, 0x10), 266 DEFINE_RES_IRQ(142), 267 DEFINE_RES_IRQ(143), 268 }; 269 270 static struct platform_device cmt_device = { 271 .name = "sh-cmt-16", 272 .id = 0, 273 .dev = { 274 .platform_data = &cmt_platform_data, 275 }, 276 .resource = cmt_resources, 277 .num_resources = ARRAY_SIZE(cmt_resources), 278 }; 279 280 static struct resource mtu2_resources[] = { 281 DEFINE_RES_MEM(0xfffe4000, 0x400), 282 DEFINE_RES_IRQ_NAMED(146, "tgi0a"), 283 DEFINE_RES_IRQ_NAMED(153, "tgi1a"), 284 }; 285 286 static struct platform_device mtu2_device = { 287 .name = "sh-mtu2", 288 .id = -1, 289 .resource = mtu2_resources, 290 .num_resources = ARRAY_SIZE(mtu2_resources), 291 }; 292 293 static struct resource rtc_resources[] = { 294 [0] = { 295 .start = 0xffff2000, 296 .end = 0xffff2000 + 0x58 - 1, 297 .flags = IORESOURCE_IO, 298 }, 299 [1] = { 300 /* Shared Period/Carry/Alarm IRQ */ 301 .start = 231, 302 .flags = IORESOURCE_IRQ, 303 }, 304 }; 305 306 static struct platform_device rtc_device = { 307 .name = "sh-rtc", 308 .id = -1, 309 .num_resources = ARRAY_SIZE(rtc_resources), 310 .resource = rtc_resources, 311 }; 312 313 static struct platform_device *sh7203_devices[] __initdata = { 314 &scif0_device, 315 &scif1_device, 316 &scif2_device, 317 &scif3_device, 318 &cmt_device, 319 &mtu2_device, 320 &rtc_device, 321 }; 322 323 static int __init sh7203_devices_setup(void) 324 { 325 return platform_add_devices(sh7203_devices, 326 ARRAY_SIZE(sh7203_devices)); 327 } 328 arch_initcall(sh7203_devices_setup); 329 330 void __init plat_irq_setup(void) 331 { 332 register_intc_controller(&intc_desc); 333 } 334 335 static struct platform_device *sh7203_early_devices[] __initdata = { 336 &scif0_device, 337 &scif1_device, 338 &scif2_device, 339 &scif3_device, 340 &cmt_device, 341 &mtu2_device, 342 }; 343 344 #define STBCR3 0xfffe0408 345 #define STBCR4 0xfffe040c 346 347 void __init plat_early_device_setup(void) 348 { 349 /* enable CMT clock */ 350 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4); 351 352 /* enable MTU2 clock */ 353 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3); 354 355 early_platform_add_devices(sh7203_early_devices, 356 ARRAY_SIZE(sh7203_early_devices)); 357 } 358