1 /*
2  *  SH7201 setup
3  *
4  *  Copyright (C) 2008  Peter Griffin pgriffin@mpc-data.co.uk
5  *  Copyright (C) 2009  Paul Mundt
6  *
7  * This file is subject to the terms and conditions of the GNU General Public
8  * License.  See the file "COPYING" in the main directory of this archive
9  * for more details.
10  */
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_timer.h>
16 #include <linux/io.h>
17 
18 enum {
19 	UNUSED = 0,
20 
21 	/* interrupt sources */
22 	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
23 	PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
24 
25 	ADC_ADI,
26 
27 	MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
28 	MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,
29 
30 	RTC, WDT,
31 
32 	IIC30, IIC31, IIC32,
33 
34 	DMAC0_DMINT0, DMAC1_DMINT1,
35 	DMAC2_DMINT2, DMAC3_DMINT3,
36 
37 	SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
38 
39 	DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
40 	DMAC7_DMINT7,
41 
42 	RCAN0, RCAN1,
43 
44 	SSI0_SSII, SSI1_SSII,
45 
46 	TMR0, TMR1,
47 
48 	/* interrupt groups */
49 	PINT,
50 };
51 
52 static struct intc_vect vectors[] __initdata = {
53 	INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
54 	INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
55 	INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
56 	INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
57 
58 	INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
59 	INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
60 	INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
61 	INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
62 
63 	INTC_IRQ(ADC_ADI, 92),
64 
65 	INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
66 	INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),
67 
68 	INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
69 	INTC_IRQ(MTU20_VEF, 114),
70 
71 	INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
72 	INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),
73 
74 	INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
75 	INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),
76 
77 	INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
78 	INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),
79 
80 	INTC_IRQ(MTU2_TCI3V, 136),
81 
82 	INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
83 	INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),
84 
85 	INTC_IRQ(MTU2_TCI4V, 144),
86 
87 	INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
88 	INTC_IRQ(MTU25_UVW, 150),
89 
90 	INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
91 	INTC_IRQ(RTC, 154),
92 
93 	INTC_IRQ(WDT, 156),
94 
95 	INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
96 	INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
97 	INTC_IRQ(IIC30, 161),
98 
99 	INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
100 	INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
101 	INTC_IRQ(IIC31, 168),
102 
103 	INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
104 	INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
105 	INTC_IRQ(IIC32, 174),
106 
107 	INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
108 	INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
109 
110 	INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
111 	INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
112 	INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
113 	INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
114 	INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
115 	INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
116 	INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
117 	INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
118 	INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
119 	INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
120 	INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
121 	INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
122 	INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
123 	INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
124 	INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
125 	INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),
126 
127 	INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
128 	INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
129 	INTC_IRQ(DMAC7_DMINT7, 219),
130 
131 	INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
132 	INTC_IRQ(RCAN0, 230),
133 	INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),
134 
135 	INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
136 	INTC_IRQ(RCAN1, 236),
137 	INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),
138 
139 	INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
140 
141 	INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
142 	INTC_IRQ(TMR0, 248),
143 
144 	INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
145 	INTC_IRQ(TMR1, 254),
146 };
147 
148 static struct intc_group groups[] __initdata = {
149 	INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
150 		   PINT4, PINT5, PINT6, PINT7),
151 };
152 
153 static struct intc_prio_reg prio_registers[] __initdata = {
154 	{ 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
155 	{ 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
156 	{ 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } },
157 	{ 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } },
158 	{ 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU,  MTU23_ABCD } },
159 	{ 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } },
160 
161 	{ 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
162 	{ 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
163 	{ 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
164 	{ 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
165 	{ 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4  } },
166 	{ 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
167 	{ 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } },
168 	{ 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } },
169 };
170 
171 static struct intc_mask_reg mask_registers[] __initdata = {
172 	{ 0xfffe9408, 0, 16, /* PINTER */
173 	  { 0, 0, 0, 0, 0, 0, 0, 0,
174 	    PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
175 };
176 
177 static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
178 			 mask_registers, prio_registers, NULL);
179 
180 static struct plat_sci_port scif0_platform_data = {
181 	.scscr		= SCSCR_REIE,
182 	.type		= PORT_SCIF,
183 };
184 
185 static struct resource scif0_resources[] = {
186 	DEFINE_RES_MEM(0xfffe8000, 0x100),
187 	DEFINE_RES_IRQ(180),
188 };
189 
190 static struct platform_device scif0_device = {
191 	.name		= "sh-sci",
192 	.id		= 0,
193 	.resource	= scif0_resources,
194 	.num_resources	= ARRAY_SIZE(scif0_resources),
195 	.dev		= {
196 		.platform_data	= &scif0_platform_data,
197 	},
198 };
199 
200 static struct plat_sci_port scif1_platform_data = {
201 	.scscr		= SCSCR_REIE,
202 	.type		= PORT_SCIF,
203 };
204 
205 static struct resource scif1_resources[] = {
206 	DEFINE_RES_MEM(0xfffe8800, 0x100),
207 	DEFINE_RES_IRQ(184),
208 };
209 
210 static struct platform_device scif1_device = {
211 	.name		= "sh-sci",
212 	.id		= 1,
213 	.resource	= scif1_resources,
214 	.num_resources	= ARRAY_SIZE(scif1_resources),
215 	.dev		= {
216 		.platform_data	= &scif1_platform_data,
217 	},
218 };
219 
220 static struct plat_sci_port scif2_platform_data = {
221 	.scscr		= SCSCR_REIE,
222 	.type		= PORT_SCIF,
223 };
224 
225 static struct resource scif2_resources[] = {
226 	DEFINE_RES_MEM(0xfffe9000, 0x100),
227 	DEFINE_RES_IRQ(188),
228 };
229 
230 static struct platform_device scif2_device = {
231 	.name		= "sh-sci",
232 	.id		= 2,
233 	.resource	= scif2_resources,
234 	.num_resources	= ARRAY_SIZE(scif2_resources),
235 	.dev		= {
236 		.platform_data	= &scif2_platform_data,
237 	},
238 };
239 
240 static struct plat_sci_port scif3_platform_data = {
241 	.scscr		= SCSCR_REIE,
242 	.type		= PORT_SCIF,
243 };
244 
245 static struct resource scif3_resources[] = {
246 	DEFINE_RES_MEM(0xfffe9800, 0x100),
247 	DEFINE_RES_IRQ(192),
248 };
249 
250 static struct platform_device scif3_device = {
251 	.name		= "sh-sci",
252 	.id		= 3,
253 	.resource	= scif3_resources,
254 	.num_resources	= ARRAY_SIZE(scif3_resources),
255 	.dev		= {
256 		.platform_data	= &scif3_platform_data,
257 	},
258 };
259 
260 static struct plat_sci_port scif4_platform_data = {
261 	.scscr		= SCSCR_REIE,
262 	.type		= PORT_SCIF,
263 };
264 
265 static struct resource scif4_resources[] = {
266 	DEFINE_RES_MEM(0xfffea000, 0x100),
267 	DEFINE_RES_IRQ(196),
268 };
269 
270 static struct platform_device scif4_device = {
271 	.name		= "sh-sci",
272 	.id		= 4,
273 	.resource	= scif4_resources,
274 	.num_resources	= ARRAY_SIZE(scif4_resources),
275 	.dev		= {
276 		.platform_data	= &scif4_platform_data,
277 	},
278 };
279 
280 static struct plat_sci_port scif5_platform_data = {
281 	.scscr		= SCSCR_REIE,
282 	.type		= PORT_SCIF,
283 };
284 
285 static struct resource scif5_resources[] = {
286 	DEFINE_RES_MEM(0xfffea800, 0x100),
287 	DEFINE_RES_IRQ(200),
288 };
289 
290 static struct platform_device scif5_device = {
291 	.name		= "sh-sci",
292 	.id		= 5,
293 	.resource	= scif5_resources,
294 	.num_resources	= ARRAY_SIZE(scif5_resources),
295 	.dev		= {
296 		.platform_data	= &scif5_platform_data,
297 	},
298 };
299 
300 static struct plat_sci_port scif6_platform_data = {
301 	.scscr		= SCSCR_REIE,
302 	.type		= PORT_SCIF,
303 };
304 
305 static struct resource scif6_resources[] = {
306 	DEFINE_RES_MEM(0xfffeb000, 0x100),
307 	DEFINE_RES_IRQ(204),
308 };
309 
310 static struct platform_device scif6_device = {
311 	.name		= "sh-sci",
312 	.id		= 6,
313 	.resource	= scif6_resources,
314 	.num_resources	= ARRAY_SIZE(scif6_resources),
315 	.dev		= {
316 		.platform_data	= &scif6_platform_data,
317 	},
318 };
319 
320 static struct plat_sci_port scif7_platform_data = {
321 	.scscr		= SCSCR_REIE,
322 	.type		= PORT_SCIF,
323 };
324 
325 static struct resource scif7_resources[] = {
326 	DEFINE_RES_MEM(0xfffeb800, 0x100),
327 	DEFINE_RES_IRQ(208),
328 };
329 
330 static struct platform_device scif7_device = {
331 	.name		= "sh-sci",
332 	.id		= 7,
333 	.resource	= scif7_resources,
334 	.num_resources	= ARRAY_SIZE(scif7_resources),
335 	.dev		= {
336 		.platform_data	= &scif7_platform_data,
337 	},
338 };
339 
340 static struct resource rtc_resources[] = {
341 	[0] = {
342 		.start	= 0xffff0800,
343 		.end	= 0xffff2000 + 0x58 - 1,
344 		.flags	= IORESOURCE_IO,
345 	},
346 	[1] = {
347 		/* Shared Period/Carry/Alarm IRQ */
348 		.start	= 152,
349 		.flags	= IORESOURCE_IRQ,
350 	},
351 };
352 
353 static struct platform_device rtc_device = {
354 	.name		= "sh-rtc",
355 	.id		= -1,
356 	.num_resources	= ARRAY_SIZE(rtc_resources),
357 	.resource	= rtc_resources,
358 };
359 
360 static struct resource mtu2_resources[] = {
361 	DEFINE_RES_MEM(0xfffe4000, 0x400),
362 	DEFINE_RES_IRQ_NAMED(108, "tgi0a"),
363 	DEFINE_RES_IRQ_NAMED(116, "tgi1a"),
364 	DEFINE_RES_IRQ_NAMED(124, "tgi1b"),
365 };
366 
367 static struct platform_device mtu2_device = {
368 	.name		= "sh-mtu2",
369 	.id		= -1,
370 	.resource	= mtu2_resources,
371 	.num_resources	= ARRAY_SIZE(mtu2_resources),
372 };
373 
374 static struct platform_device *sh7201_devices[] __initdata = {
375 	&scif0_device,
376 	&scif1_device,
377 	&scif2_device,
378 	&scif3_device,
379 	&scif4_device,
380 	&scif5_device,
381 	&scif6_device,
382 	&scif7_device,
383 	&rtc_device,
384 	&mtu2_device,
385 };
386 
387 static int __init sh7201_devices_setup(void)
388 {
389 	return platform_add_devices(sh7201_devices,
390 				    ARRAY_SIZE(sh7201_devices));
391 }
392 arch_initcall(sh7201_devices_setup);
393 
394 void __init plat_irq_setup(void)
395 {
396 	register_intc_controller(&intc_desc);
397 }
398 
399 static struct platform_device *sh7201_early_devices[] __initdata = {
400 	&scif0_device,
401 	&scif1_device,
402 	&scif2_device,
403 	&scif3_device,
404 	&scif4_device,
405 	&scif5_device,
406 	&scif6_device,
407 	&scif7_device,
408 	&mtu2_device,
409 };
410 
411 #define STBCR3 0xfffe0408
412 
413 void __init plat_early_device_setup(void)
414 {
415 	/* enable MTU2 clock */
416 	__raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
417 
418 	early_platform_add_devices(sh7201_early_devices,
419 				   ARRAY_SIZE(sh7201_early_devices));
420 }
421