1 /* 2 * SH7201 setup 3 * 4 * Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/platform_device.h> 12 #include <linux/init.h> 13 #include <linux/serial.h> 14 #include <linux/serial_sci.h> 15 16 enum { 17 UNUSED = 0, 18 19 /* interrupt sources */ 20 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 21 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 22 23 ADC_ADI, 24 25 MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU, 26 MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V, 27 28 RTC, WDT, 29 30 IIC30, IIC31, IIC32, 31 32 DMAC0_DMINT0, DMAC1_DMINT1, 33 DMAC2_DMINT2, DMAC3_DMINT3, 34 35 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7, 36 37 DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6, 38 DMAC7_DMINT7, 39 40 RCAN0, RCAN1, 41 42 SSI0_SSII, SSI1_SSII, 43 44 TMR0, TMR1, 45 46 /* interrupt groups */ 47 PINT, 48 }; 49 50 static struct intc_vect vectors[] __initdata = { 51 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), 52 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 53 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), 54 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), 55 56 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), 57 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 58 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 59 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 60 61 INTC_IRQ(ADC_ADI, 92), 62 63 INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109), 64 INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111), 65 66 INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113), 67 INTC_IRQ(MTU20_VEF, 114), 68 69 INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117), 70 INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121), 71 72 INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125), 73 INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129), 74 75 INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133), 76 INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135), 77 78 INTC_IRQ(MTU2_TCI3V, 136), 79 80 INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141), 81 INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143), 82 83 INTC_IRQ(MTU2_TCI4V, 144), 84 85 INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149), 86 INTC_IRQ(MTU25_UVW, 150), 87 88 INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153), 89 INTC_IRQ(RTC, 154), 90 91 INTC_IRQ(WDT, 156), 92 93 INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158), 94 INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160), 95 INTC_IRQ(IIC30, 161), 96 97 INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165), 98 INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167), 99 INTC_IRQ(IIC31, 168), 100 101 INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171), 102 INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173), 103 INTC_IRQ(IIC32, 174), 104 105 INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177), 106 INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179), 107 108 INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181), 109 INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183), 110 INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185), 111 INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187), 112 INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189), 113 INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191), 114 INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193), 115 INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195), 116 INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197), 117 INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199), 118 INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201), 119 INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203), 120 INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205), 121 INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207), 122 INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209), 123 INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211), 124 125 INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216), 126 INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218), 127 INTC_IRQ(DMAC7_DMINT7, 219), 128 129 INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229), 130 INTC_IRQ(RCAN0, 230), 131 INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232), 132 133 INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235), 134 INTC_IRQ(RCAN1, 236), 135 INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238), 136 137 INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245), 138 139 INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247), 140 INTC_IRQ(TMR0, 248), 141 142 INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253), 143 INTC_IRQ(TMR1, 254), 144 }; 145 146 static struct intc_group groups[] __initdata = { 147 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 148 PINT4, PINT5, PINT6, PINT7), 149 }; 150 151 static struct intc_prio_reg prio_registers[] __initdata = { 152 { 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 153 { 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 154 { 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } }, 155 { 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } }, 156 { 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } }, 157 { 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } }, 158 159 { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } }, 160 { 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } }, 161 { 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } }, 162 { 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } }, 163 { 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } }, 164 { 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } }, 165 { 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } }, 166 { 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } }, 167 }; 168 169 static struct intc_mask_reg mask_registers[] __initdata = { 170 { 0xfffe9408, 0, 16, /* PINTER */ 171 { 0, 0, 0, 0, 0, 0, 0, 0, 172 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, 173 }; 174 175 static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups, 176 mask_registers, prio_registers, NULL); 177 178 static struct plat_sci_port sci_platform_data[] = { 179 { 180 .mapbase = 0xfffe8000, 181 .flags = UPF_BOOT_AUTOCONF, 182 .type = PORT_SCIF, 183 .irqs = { 180, 180, 180, 180 } 184 }, { 185 .mapbase = 0xfffe8800, 186 .flags = UPF_BOOT_AUTOCONF, 187 .type = PORT_SCIF, 188 .irqs = { 184, 184, 184, 184 } 189 }, { 190 .mapbase = 0xfffe9000, 191 .flags = UPF_BOOT_AUTOCONF, 192 .type = PORT_SCIF, 193 .irqs = { 188, 188, 188, 188 } 194 }, { 195 .mapbase = 0xfffe9800, 196 .flags = UPF_BOOT_AUTOCONF, 197 .type = PORT_SCIF, 198 .irqs = { 192, 192, 192, 192 } 199 }, { 200 .mapbase = 0xfffea000, 201 .flags = UPF_BOOT_AUTOCONF, 202 .type = PORT_SCIF, 203 .irqs = { 196, 196, 196, 196 } 204 }, { 205 .mapbase = 0xfffea800, 206 .flags = UPF_BOOT_AUTOCONF, 207 .type = PORT_SCIF, 208 .irqs = { 200, 200, 200, 200 } 209 }, { 210 .mapbase = 0xfffeb000, 211 .flags = UPF_BOOT_AUTOCONF, 212 .type = PORT_SCIF, 213 .irqs = { 204, 204, 204, 204 } 214 }, { 215 .mapbase = 0xfffeb800, 216 .flags = UPF_BOOT_AUTOCONF, 217 .type = PORT_SCIF, 218 .irqs = { 208, 208, 208, 208 } 219 }, { 220 .flags = 0, 221 } 222 }; 223 224 static struct platform_device sci_device = { 225 .name = "sh-sci", 226 .id = -1, 227 .dev = { 228 .platform_data = sci_platform_data, 229 }, 230 }; 231 232 static struct resource rtc_resources[] = { 233 [0] = { 234 .start = 0xffff0800, 235 .end = 0xffff2000 + 0x58 - 1, 236 .flags = IORESOURCE_IO, 237 }, 238 [1] = { 239 /* Shared Period/Carry/Alarm IRQ */ 240 .start = 152, 241 .flags = IORESOURCE_IRQ, 242 }, 243 }; 244 245 static struct platform_device rtc_device = { 246 .name = "sh-rtc", 247 .id = -1, 248 .num_resources = ARRAY_SIZE(rtc_resources), 249 .resource = rtc_resources, 250 }; 251 252 static struct platform_device *sh7201_devices[] __initdata = { 253 &sci_device, 254 &rtc_device, 255 }; 256 257 static int __init sh7201_devices_setup(void) 258 { 259 return platform_add_devices(sh7201_devices, 260 ARRAY_SIZE(sh7201_devices)); 261 } 262 __initcall(sh7201_devices_setup); 263 264 void __init plat_irq_setup(void) 265 { 266 register_intc_controller(&intc_desc); 267 } 268