1 /* 2 * Renesas MX-G (R8A03022BG) Setup 3 * 4 * Copyright (C) 2008, 2009 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/serial_sci.h> 14 15 enum { 16 UNUSED = 0, 17 18 /* interrupt sources */ 19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 20 IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15, 21 22 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 23 SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1, 24 25 SCIF0, SCIF1, 26 27 MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5 28 MTU2_TGI3B, MTU2_TGI3C, 29 30 /* interrupt groups */ 31 PINT, 32 }; 33 34 static struct intc_vect vectors[] __initdata = { 35 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), 36 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 37 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), 38 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), 39 INTC_IRQ(IRQ8, 72), INTC_IRQ(IRQ9, 73), 40 INTC_IRQ(IRQ10, 74), INTC_IRQ(IRQ11, 75), 41 INTC_IRQ(IRQ12, 76), INTC_IRQ(IRQ13, 77), 42 INTC_IRQ(IRQ14, 78), INTC_IRQ(IRQ15, 79), 43 44 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), 45 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 46 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 47 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 48 49 INTC_IRQ(SINT8, 94), INTC_IRQ(SINT7, 95), 50 INTC_IRQ(SINT6, 96), INTC_IRQ(SINT5, 97), 51 INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99), 52 INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101), 53 54 INTC_IRQ(SCIF0, 220), INTC_IRQ(SCIF0, 221), 55 INTC_IRQ(SCIF0, 222), INTC_IRQ(SCIF0, 223), 56 INTC_IRQ(SCIF1, 224), INTC_IRQ(SCIF1, 225), 57 INTC_IRQ(SCIF1, 226), INTC_IRQ(SCIF1, 227), 58 59 INTC_IRQ(MTU2_GROUP1, 228), INTC_IRQ(MTU2_GROUP1, 229), 60 INTC_IRQ(MTU2_GROUP1, 230), INTC_IRQ(MTU2_GROUP1, 231), 61 INTC_IRQ(MTU2_GROUP1, 232), INTC_IRQ(MTU2_GROUP1, 233), 62 63 INTC_IRQ(MTU2_GROUP2, 234), INTC_IRQ(MTU2_GROUP2, 235), 64 INTC_IRQ(MTU2_GROUP2, 236), INTC_IRQ(MTU2_GROUP2, 237), 65 INTC_IRQ(MTU2_GROUP2, 238), INTC_IRQ(MTU2_GROUP2, 239), 66 67 INTC_IRQ(MTU2_GROUP3, 240), INTC_IRQ(MTU2_GROUP3, 241), 68 INTC_IRQ(MTU2_GROUP3, 242), INTC_IRQ(MTU2_GROUP3, 243), 69 70 INTC_IRQ(MTU2_TGI3B, 244), 71 INTC_IRQ(MTU2_TGI3C, 245), 72 73 INTC_IRQ(MTU2_GROUP4, 246), INTC_IRQ(MTU2_GROUP4, 247), 74 INTC_IRQ(MTU2_GROUP4, 248), INTC_IRQ(MTU2_GROUP4, 249), 75 INTC_IRQ(MTU2_GROUP4, 250), INTC_IRQ(MTU2_GROUP4, 251), 76 77 INTC_IRQ(MTU2_GROUP5, 252), INTC_IRQ(MTU2_GROUP5, 253), 78 INTC_IRQ(MTU2_GROUP5, 254), INTC_IRQ(MTU2_GROUP5, 255), 79 }; 80 81 static struct intc_group groups[] __initdata = { 82 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 83 PINT4, PINT5, PINT6, PINT7), 84 }; 85 86 static struct intc_prio_reg prio_registers[] __initdata = { 87 { 0xfffd9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 88 { 0xfffd941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 89 { 0xfffd941c, 0, 16, 4, /* IPR03 */ { IRQ8, IRQ9, IRQ10, IRQ11 } }, 90 { 0xfffd941e, 0, 16, 4, /* IPR04 */ { IRQ12, IRQ13, IRQ14, IRQ15 } }, 91 { 0xfffd9420, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } }, 92 { 0xfffd9800, 0, 16, 4, /* IPR06 */ { } }, 93 { 0xfffd9802, 0, 16, 4, /* IPR07 */ { } }, 94 { 0xfffd9804, 0, 16, 4, /* IPR08 */ { } }, 95 { 0xfffd9806, 0, 16, 4, /* IPR09 */ { } }, 96 { 0xfffd9808, 0, 16, 4, /* IPR10 */ { } }, 97 { 0xfffd980a, 0, 16, 4, /* IPR11 */ { } }, 98 { 0xfffd980c, 0, 16, 4, /* IPR12 */ { } }, 99 { 0xfffd980e, 0, 16, 4, /* IPR13 */ { } }, 100 { 0xfffd9810, 0, 16, 4, /* IPR14 */ { 0, 0, 0, SCIF0 } }, 101 { 0xfffd9812, 0, 16, 4, /* IPR15 */ 102 { SCIF1, MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3 } }, 103 { 0xfffd9814, 0, 16, 4, /* IPR16 */ 104 { MTU2_TGI3B, MTU2_TGI3C, MTU2_GROUP4, MTU2_GROUP5 } }, 105 }; 106 107 static struct intc_mask_reg mask_registers[] __initdata = { 108 { 0xfffd9408, 0, 16, /* PINTER */ 109 { 0, 0, 0, 0, 0, 0, 0, 0, 110 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, 111 }; 112 113 static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups, 114 mask_registers, prio_registers, NULL); 115 116 static struct plat_sci_port sci_platform_data[] = { 117 { 118 .mapbase = 0xff804000, 119 .flags = UPF_BOOT_AUTOCONF, 120 .type = PORT_SCIF, 121 .irqs = { 220, 220, 220, 220 }, 122 }, { 123 .flags = 0, 124 } 125 }; 126 127 static struct platform_device sci_device = { 128 .name = "sh-sci", 129 .id = -1, 130 .dev = { 131 .platform_data = sci_platform_data, 132 }, 133 }; 134 135 static struct platform_device *mxg_devices[] __initdata = { 136 &sci_device, 137 }; 138 139 static int __init mxg_devices_setup(void) 140 { 141 return platform_add_devices(mxg_devices, 142 ARRAY_SIZE(mxg_devices)); 143 } 144 __initcall(mxg_devices_setup); 145 146 void __init plat_irq_setup(void) 147 { 148 register_intc_controller(&intc_desc); 149 } 150