1 /* 2 * Renesas MX-G (R8A03022BG) Setup 3 * 4 * Copyright (C) 2008, 2009 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/platform_device.h> 11 #include <linux/init.h> 12 #include <linux/serial.h> 13 #include <linux/serial_sci.h> 14 #include <linux/sh_timer.h> 15 16 enum { 17 UNUSED = 0, 18 19 /* interrupt sources */ 20 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 21 IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15, 22 23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 24 SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1, 25 26 SCIF0, SCIF1, 27 28 MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5, 29 MTU2_TGI3B, MTU2_TGI3C, 30 31 /* interrupt groups */ 32 PINT, 33 }; 34 35 static struct intc_vect vectors[] __initdata = { 36 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), 37 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 38 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), 39 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), 40 INTC_IRQ(IRQ8, 72), INTC_IRQ(IRQ9, 73), 41 INTC_IRQ(IRQ10, 74), INTC_IRQ(IRQ11, 75), 42 INTC_IRQ(IRQ12, 76), INTC_IRQ(IRQ13, 77), 43 INTC_IRQ(IRQ14, 78), INTC_IRQ(IRQ15, 79), 44 45 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), 46 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 47 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 48 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 49 50 INTC_IRQ(SINT8, 94), INTC_IRQ(SINT7, 95), 51 INTC_IRQ(SINT6, 96), INTC_IRQ(SINT5, 97), 52 INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99), 53 INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101), 54 55 INTC_IRQ(SCIF0, 220), INTC_IRQ(SCIF0, 221), 56 INTC_IRQ(SCIF0, 222), INTC_IRQ(SCIF0, 223), 57 INTC_IRQ(SCIF1, 224), INTC_IRQ(SCIF1, 225), 58 INTC_IRQ(SCIF1, 226), INTC_IRQ(SCIF1, 227), 59 60 INTC_IRQ(MTU2_GROUP1, 228), INTC_IRQ(MTU2_GROUP1, 229), 61 INTC_IRQ(MTU2_GROUP1, 230), INTC_IRQ(MTU2_GROUP1, 231), 62 INTC_IRQ(MTU2_GROUP1, 232), INTC_IRQ(MTU2_GROUP1, 233), 63 64 INTC_IRQ(MTU2_GROUP2, 234), INTC_IRQ(MTU2_GROUP2, 235), 65 INTC_IRQ(MTU2_GROUP2, 236), INTC_IRQ(MTU2_GROUP2, 237), 66 INTC_IRQ(MTU2_GROUP2, 238), INTC_IRQ(MTU2_GROUP2, 239), 67 68 INTC_IRQ(MTU2_GROUP3, 240), INTC_IRQ(MTU2_GROUP3, 241), 69 INTC_IRQ(MTU2_GROUP3, 242), INTC_IRQ(MTU2_GROUP3, 243), 70 71 INTC_IRQ(MTU2_TGI3B, 244), 72 INTC_IRQ(MTU2_TGI3C, 245), 73 74 INTC_IRQ(MTU2_GROUP4, 246), INTC_IRQ(MTU2_GROUP4, 247), 75 INTC_IRQ(MTU2_GROUP4, 248), INTC_IRQ(MTU2_GROUP4, 249), 76 INTC_IRQ(MTU2_GROUP4, 250), INTC_IRQ(MTU2_GROUP4, 251), 77 78 INTC_IRQ(MTU2_GROUP5, 252), INTC_IRQ(MTU2_GROUP5, 253), 79 INTC_IRQ(MTU2_GROUP5, 254), INTC_IRQ(MTU2_GROUP5, 255), 80 }; 81 82 static struct intc_group groups[] __initdata = { 83 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 84 PINT4, PINT5, PINT6, PINT7), 85 }; 86 87 static struct intc_prio_reg prio_registers[] __initdata = { 88 { 0xfffd9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 89 { 0xfffd941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 90 { 0xfffd941c, 0, 16, 4, /* IPR03 */ { IRQ8, IRQ9, IRQ10, IRQ11 } }, 91 { 0xfffd941e, 0, 16, 4, /* IPR04 */ { IRQ12, IRQ13, IRQ14, IRQ15 } }, 92 { 0xfffd9420, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } }, 93 { 0xfffd9800, 0, 16, 4, /* IPR06 */ { } }, 94 { 0xfffd9802, 0, 16, 4, /* IPR07 */ { } }, 95 { 0xfffd9804, 0, 16, 4, /* IPR08 */ { } }, 96 { 0xfffd9806, 0, 16, 4, /* IPR09 */ { } }, 97 { 0xfffd9808, 0, 16, 4, /* IPR10 */ { } }, 98 { 0xfffd980a, 0, 16, 4, /* IPR11 */ { } }, 99 { 0xfffd980c, 0, 16, 4, /* IPR12 */ { } }, 100 { 0xfffd980e, 0, 16, 4, /* IPR13 */ { } }, 101 { 0xfffd9810, 0, 16, 4, /* IPR14 */ { 0, 0, 0, SCIF0 } }, 102 { 0xfffd9812, 0, 16, 4, /* IPR15 */ 103 { SCIF1, MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3 } }, 104 { 0xfffd9814, 0, 16, 4, /* IPR16 */ 105 { MTU2_TGI3B, MTU2_TGI3C, MTU2_GROUP4, MTU2_GROUP5 } }, 106 }; 107 108 static struct intc_mask_reg mask_registers[] __initdata = { 109 { 0xfffd9408, 0, 16, /* PINTER */ 110 { 0, 0, 0, 0, 0, 0, 0, 0, 111 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, 112 }; 113 114 static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups, 115 mask_registers, prio_registers, NULL); 116 117 static struct sh_timer_config mtu2_0_platform_data = { 118 .channel_offset = -0x80, 119 .timer_bit = 0, 120 .clockevent_rating = 200, 121 }; 122 123 static struct resource mtu2_0_resources[] = { 124 [0] = { 125 .start = 0xff801300, 126 .end = 0xff801326, 127 .flags = IORESOURCE_MEM, 128 }, 129 [1] = { 130 .start = 228, 131 .flags = IORESOURCE_IRQ, 132 }, 133 }; 134 135 static struct platform_device mtu2_0_device = { 136 .name = "sh_mtu2", 137 .id = 0, 138 .dev = { 139 .platform_data = &mtu2_0_platform_data, 140 }, 141 .resource = mtu2_0_resources, 142 .num_resources = ARRAY_SIZE(mtu2_0_resources), 143 }; 144 145 static struct sh_timer_config mtu2_1_platform_data = { 146 .channel_offset = -0x100, 147 .timer_bit = 1, 148 .clockevent_rating = 200, 149 }; 150 151 static struct resource mtu2_1_resources[] = { 152 [0] = { 153 .start = 0xff801380, 154 .end = 0xff801390, 155 .flags = IORESOURCE_MEM, 156 }, 157 [1] = { 158 .start = 234, 159 .flags = IORESOURCE_IRQ, 160 }, 161 }; 162 163 static struct platform_device mtu2_1_device = { 164 .name = "sh_mtu2", 165 .id = 1, 166 .dev = { 167 .platform_data = &mtu2_1_platform_data, 168 }, 169 .resource = mtu2_1_resources, 170 .num_resources = ARRAY_SIZE(mtu2_1_resources), 171 }; 172 173 static struct sh_timer_config mtu2_2_platform_data = { 174 .channel_offset = 0x80, 175 .timer_bit = 2, 176 .clockevent_rating = 200, 177 }; 178 179 static struct resource mtu2_2_resources[] = { 180 [0] = { 181 .start = 0xff801000, 182 .end = 0xff80100a, 183 .flags = IORESOURCE_MEM, 184 }, 185 [1] = { 186 .start = 240, 187 .flags = IORESOURCE_IRQ, 188 }, 189 }; 190 191 static struct platform_device mtu2_2_device = { 192 .name = "sh_mtu2", 193 .id = 2, 194 .dev = { 195 .platform_data = &mtu2_2_platform_data, 196 }, 197 .resource = mtu2_2_resources, 198 .num_resources = ARRAY_SIZE(mtu2_2_resources), 199 }; 200 201 static struct plat_sci_port scif0_platform_data = { 202 .mapbase = 0xff804000, 203 .flags = UPF_BOOT_AUTOCONF, 204 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 205 .scbrr_algo_id = SCBRR_ALGO_2, 206 .type = PORT_SCIF, 207 .irqs = { 220, 220, 220, 220 }, 208 }; 209 210 static struct platform_device scif0_device = { 211 .name = "sh-sci", 212 .id = 0, 213 .dev = { 214 .platform_data = &scif0_platform_data, 215 }, 216 }; 217 218 static struct platform_device *mxg_devices[] __initdata = { 219 &scif0_device, 220 &mtu2_0_device, 221 &mtu2_1_device, 222 &mtu2_2_device, 223 }; 224 225 static int __init mxg_devices_setup(void) 226 { 227 return platform_add_devices(mxg_devices, 228 ARRAY_SIZE(mxg_devices)); 229 } 230 arch_initcall(mxg_devices_setup); 231 232 void __init plat_irq_setup(void) 233 { 234 register_intc_controller(&intc_desc); 235 } 236 237 static struct platform_device *mxg_early_devices[] __initdata = { 238 &scif0_device, 239 &mtu2_0_device, 240 &mtu2_1_device, 241 &mtu2_2_device, 242 }; 243 244 void __init plat_early_device_setup(void) 245 { 246 early_platform_add_devices(mxg_early_devices, 247 ARRAY_SIZE(mxg_early_devices)); 248 } 249