xref: /openbmc/linux/arch/sh/kernel/cpu/sh2a/probe.c (revision 293d5b43)
1 /*
2  * arch/sh/kernel/cpu/sh2a/probe.c
3  *
4  * CPU Subtype Probing for SH-2A.
5  *
6  * Copyright (C) 2004 - 2007  Paul Mundt
7  *
8  * This file is subject to the terms and conditions of the GNU General Public
9  * License.  See the file "COPYING" in the main directory of this archive
10  * for more details.
11  */
12 #include <linux/init.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 
16 void cpu_probe(void)
17 {
18 	boot_cpu_data.family			= CPU_FAMILY_SH2A;
19 
20 	/* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */
21 	boot_cpu_data.flags			|= CPU_HAS_OP32;
22 
23 #if defined(CONFIG_CPU_SUBTYPE_SH7201)
24 	boot_cpu_data.type			= CPU_SH7201;
25 	boot_cpu_data.flags			|= CPU_HAS_FPU;
26 #elif defined(CONFIG_CPU_SUBTYPE_SH7203)
27 	boot_cpu_data.type			= CPU_SH7203;
28 	boot_cpu_data.flags			|= CPU_HAS_FPU;
29 #elif defined(CONFIG_CPU_SUBTYPE_SH7263)
30 	boot_cpu_data.type			= CPU_SH7263;
31 	boot_cpu_data.flags			|= CPU_HAS_FPU;
32 #elif defined(CONFIG_CPU_SUBTYPE_SH7264)
33 	boot_cpu_data.type			= CPU_SH7264;
34 	boot_cpu_data.flags			|= CPU_HAS_FPU;
35 #elif defined(CONFIG_CPU_SUBTYPE_SH7269)
36 	boot_cpu_data.type			= CPU_SH7269;
37 	boot_cpu_data.flags			|= CPU_HAS_FPU;
38 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
39 	boot_cpu_data.type			= CPU_SH7206;
40 	boot_cpu_data.flags			|= CPU_HAS_DSP;
41 #elif defined(CONFIG_CPU_SUBTYPE_MXG)
42 	boot_cpu_data.type			= CPU_MXG;
43 	boot_cpu_data.flags			|= CPU_HAS_DSP;
44 #endif
45 
46 	boot_cpu_data.dcache.ways		= 4;
47 	boot_cpu_data.dcache.way_incr		= (1 << 11);
48 	boot_cpu_data.dcache.sets		= 128;
49 	boot_cpu_data.dcache.entry_shift	= 4;
50 	boot_cpu_data.dcache.linesz		= L1_CACHE_BYTES;
51 	boot_cpu_data.dcache.flags		= 0;
52 
53 	/*
54 	 * The icache is the same as the dcache as far as this setup is
55 	 * concerned. The only real difference in hardware is that the icache
56 	 * lacks the U bit that the dcache has, none of this has any bearing
57 	 * on the cache info.
58 	 */
59 	boot_cpu_data.icache		= boot_cpu_data.dcache;
60 }
61