1234a0538SKuninori Morimoto // SPDX-License-Identifier: GPL-2.0
20b25b7c8SPhil Edworthy /*
30b25b7c8SPhil Edworthy * arch/sh/kernel/cpu/sh2a/clock-sh7269.c
40b25b7c8SPhil Edworthy *
50b25b7c8SPhil Edworthy * SH7269 clock framework support
60b25b7c8SPhil Edworthy *
70b25b7c8SPhil Edworthy * Copyright (C) 2012 Phil Edworthy
80b25b7c8SPhil Edworthy */
90b25b7c8SPhil Edworthy #include <linux/init.h>
100b25b7c8SPhil Edworthy #include <linux/kernel.h>
110b25b7c8SPhil Edworthy #include <linux/io.h>
120b25b7c8SPhil Edworthy #include <linux/clkdev.h>
130b25b7c8SPhil Edworthy #include <asm/clock.h>
140b25b7c8SPhil Edworthy
150b25b7c8SPhil Edworthy /* SH7269 registers */
160b25b7c8SPhil Edworthy #define FRQCR 0xfffe0010
170b25b7c8SPhil Edworthy #define STBCR3 0xfffe0408
180b25b7c8SPhil Edworthy #define STBCR4 0xfffe040c
190b25b7c8SPhil Edworthy #define STBCR5 0xfffe0410
200b25b7c8SPhil Edworthy #define STBCR6 0xfffe0414
210b25b7c8SPhil Edworthy #define STBCR7 0xfffe0418
220b25b7c8SPhil Edworthy
230b25b7c8SPhil Edworthy #define PLL_RATE 20
240b25b7c8SPhil Edworthy
250b25b7c8SPhil Edworthy /* Fixed 32 KHz root clock for RTC */
260b25b7c8SPhil Edworthy static struct clk r_clk = {
270b25b7c8SPhil Edworthy .rate = 32768,
280b25b7c8SPhil Edworthy };
290b25b7c8SPhil Edworthy
300b25b7c8SPhil Edworthy /*
310b25b7c8SPhil Edworthy * Default rate for the root input clock, reset this with clk_set_rate()
320b25b7c8SPhil Edworthy * from the platform code.
330b25b7c8SPhil Edworthy */
340b25b7c8SPhil Edworthy static struct clk extal_clk = {
350b25b7c8SPhil Edworthy .rate = 13340000,
360b25b7c8SPhil Edworthy };
370b25b7c8SPhil Edworthy
pll_recalc(struct clk * clk)380b25b7c8SPhil Edworthy static unsigned long pll_recalc(struct clk *clk)
390b25b7c8SPhil Edworthy {
400b25b7c8SPhil Edworthy return clk->parent->rate * PLL_RATE;
410b25b7c8SPhil Edworthy }
420b25b7c8SPhil Edworthy
430b25b7c8SPhil Edworthy static struct sh_clk_ops pll_clk_ops = {
440b25b7c8SPhil Edworthy .recalc = pll_recalc,
450b25b7c8SPhil Edworthy };
460b25b7c8SPhil Edworthy
470b25b7c8SPhil Edworthy static struct clk pll_clk = {
480b25b7c8SPhil Edworthy .ops = &pll_clk_ops,
490b25b7c8SPhil Edworthy .parent = &extal_clk,
500b25b7c8SPhil Edworthy .flags = CLK_ENABLE_ON_INIT,
510b25b7c8SPhil Edworthy };
520b25b7c8SPhil Edworthy
peripheral0_recalc(struct clk * clk)530b25b7c8SPhil Edworthy static unsigned long peripheral0_recalc(struct clk *clk)
540b25b7c8SPhil Edworthy {
550b25b7c8SPhil Edworthy return clk->parent->rate / 8;
560b25b7c8SPhil Edworthy }
570b25b7c8SPhil Edworthy
580b25b7c8SPhil Edworthy static struct sh_clk_ops peripheral0_clk_ops = {
590b25b7c8SPhil Edworthy .recalc = peripheral0_recalc,
600b25b7c8SPhil Edworthy };
610b25b7c8SPhil Edworthy
620b25b7c8SPhil Edworthy static struct clk peripheral0_clk = {
630b25b7c8SPhil Edworthy .ops = &peripheral0_clk_ops,
640b25b7c8SPhil Edworthy .parent = &pll_clk,
650b25b7c8SPhil Edworthy .flags = CLK_ENABLE_ON_INIT,
660b25b7c8SPhil Edworthy };
670b25b7c8SPhil Edworthy
peripheral1_recalc(struct clk * clk)680b25b7c8SPhil Edworthy static unsigned long peripheral1_recalc(struct clk *clk)
690b25b7c8SPhil Edworthy {
700b25b7c8SPhil Edworthy return clk->parent->rate / 4;
710b25b7c8SPhil Edworthy }
720b25b7c8SPhil Edworthy
730b25b7c8SPhil Edworthy static struct sh_clk_ops peripheral1_clk_ops = {
740b25b7c8SPhil Edworthy .recalc = peripheral1_recalc,
750b25b7c8SPhil Edworthy };
760b25b7c8SPhil Edworthy
770b25b7c8SPhil Edworthy static struct clk peripheral1_clk = {
780b25b7c8SPhil Edworthy .ops = &peripheral1_clk_ops,
790b25b7c8SPhil Edworthy .parent = &pll_clk,
800b25b7c8SPhil Edworthy .flags = CLK_ENABLE_ON_INIT,
810b25b7c8SPhil Edworthy };
820b25b7c8SPhil Edworthy
830b25b7c8SPhil Edworthy struct clk *main_clks[] = {
840b25b7c8SPhil Edworthy &r_clk,
850b25b7c8SPhil Edworthy &extal_clk,
860b25b7c8SPhil Edworthy &pll_clk,
870b25b7c8SPhil Edworthy &peripheral0_clk,
880b25b7c8SPhil Edworthy &peripheral1_clk,
890b25b7c8SPhil Edworthy };
900b25b7c8SPhil Edworthy
910b25b7c8SPhil Edworthy static int div2[] = { 1, 2, 0, 4 };
920b25b7c8SPhil Edworthy
930b25b7c8SPhil Edworthy static struct clk_div_mult_table div4_div_mult_table = {
940b25b7c8SPhil Edworthy .divisors = div2,
950b25b7c8SPhil Edworthy .nr_divisors = ARRAY_SIZE(div2),
960b25b7c8SPhil Edworthy };
970b25b7c8SPhil Edworthy
980b25b7c8SPhil Edworthy static struct clk_div4_table div4_table = {
990b25b7c8SPhil Edworthy .div_mult_table = &div4_div_mult_table,
1000b25b7c8SPhil Edworthy };
1010b25b7c8SPhil Edworthy
1020b25b7c8SPhil Edworthy enum { DIV4_I, DIV4_B,
1030b25b7c8SPhil Edworthy DIV4_NR };
1040b25b7c8SPhil Edworthy
1050b25b7c8SPhil Edworthy #define DIV4(_reg, _bit, _mask, _flags) \
1060b25b7c8SPhil Edworthy SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
1070b25b7c8SPhil Edworthy
1080b25b7c8SPhil Edworthy /* The mask field specifies the div2 entries that are valid */
1090b25b7c8SPhil Edworthy struct clk div4_clks[DIV4_NR] = {
1100b25b7c8SPhil Edworthy [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
1110b25b7c8SPhil Edworthy | CLK_ENABLE_ON_INIT),
1120b25b7c8SPhil Edworthy [DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT
1130b25b7c8SPhil Edworthy | CLK_ENABLE_ON_INIT),
1140b25b7c8SPhil Edworthy };
1150b25b7c8SPhil Edworthy
1160b25b7c8SPhil Edworthy enum { MSTP72,
1170b25b7c8SPhil Edworthy MSTP60,
1180b25b7c8SPhil Edworthy MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
1190b25b7c8SPhil Edworthy MSTP35, MSTP32, MSTP30,
1200b25b7c8SPhil Edworthy MSTP_NR };
1210b25b7c8SPhil Edworthy
1220b25b7c8SPhil Edworthy static struct clk mstp_clks[MSTP_NR] = {
1230b25b7c8SPhil Edworthy [MSTP72] = SH_CLK_MSTP8(&peripheral0_clk, STBCR7, 2, 0), /* CMT */
1240b25b7c8SPhil Edworthy [MSTP60] = SH_CLK_MSTP8(&peripheral1_clk, STBCR6, 0, 0), /* USB */
1250b25b7c8SPhil Edworthy [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
1260b25b7c8SPhil Edworthy [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
1270b25b7c8SPhil Edworthy [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
1280b25b7c8SPhil Edworthy [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
1290b25b7c8SPhil Edworthy [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
1300b25b7c8SPhil Edworthy [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
1310b25b7c8SPhil Edworthy [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
1320b25b7c8SPhil Edworthy [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
1330b25b7c8SPhil Edworthy [MSTP35] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 5, 0), /* MTU2 */
1340b25b7c8SPhil Edworthy [MSTP32] = SH_CLK_MSTP8(&peripheral1_clk, STBCR3, 2, 0), /* ADC */
1350b25b7c8SPhil Edworthy [MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
1360b25b7c8SPhil Edworthy };
1370b25b7c8SPhil Edworthy
1380b25b7c8SPhil Edworthy static struct clk_lookup lookups[] = {
1390b25b7c8SPhil Edworthy /* main clocks */
1400b25b7c8SPhil Edworthy CLKDEV_CON_ID("rclk", &r_clk),
1410b25b7c8SPhil Edworthy CLKDEV_CON_ID("extal", &extal_clk),
1420b25b7c8SPhil Edworthy CLKDEV_CON_ID("pll_clk", &pll_clk),
1430b25b7c8SPhil Edworthy CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
1440b25b7c8SPhil Edworthy
1450b25b7c8SPhil Edworthy /* DIV4 clocks */
1460b25b7c8SPhil Edworthy CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
1470b25b7c8SPhil Edworthy CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
1480b25b7c8SPhil Edworthy
1490b25b7c8SPhil Edworthy /* MSTP clocks */
150fa3d39bfSLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP47]),
151fa3d39bfSLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP46]),
152fa3d39bfSLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP45]),
153fa3d39bfSLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP44]),
154fa3d39bfSLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP43]),
155fa3d39bfSLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP42]),
156fa3d39bfSLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-sci.6", &mstp_clks[MSTP41]),
157fa3d39bfSLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-sci.7", &mstp_clks[MSTP40]),
1589b17e48cSLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-cmt-16.0", &mstp_clks[MSTP72]),
1590b25b7c8SPhil Edworthy CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
1605204601cSLaurent Pinchart CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP35]),
1610b25b7c8SPhil Edworthy CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
1620b25b7c8SPhil Edworthy CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
1630b25b7c8SPhil Edworthy };
1640b25b7c8SPhil Edworthy
arch_clk_init(void)1650b25b7c8SPhil Edworthy int __init arch_clk_init(void)
1660b25b7c8SPhil Edworthy {
1670b25b7c8SPhil Edworthy int k, ret = 0;
1680b25b7c8SPhil Edworthy
1690b25b7c8SPhil Edworthy for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
1700b25b7c8SPhil Edworthy ret = clk_register(main_clks[k]);
1710b25b7c8SPhil Edworthy
1720b25b7c8SPhil Edworthy clkdev_add_table(lookups, ARRAY_SIZE(lookups));
1730b25b7c8SPhil Edworthy
1740b25b7c8SPhil Edworthy if (!ret)
1750b25b7c8SPhil Edworthy ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
1760b25b7c8SPhil Edworthy
1770b25b7c8SPhil Edworthy if (!ret)
1780b25b7c8SPhil Edworthy ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
1790b25b7c8SPhil Edworthy
1800b25b7c8SPhil Edworthy return ret;
1810b25b7c8SPhil Edworthy }
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