19d4436a6SYoshinori Sato /* 29d4436a6SYoshinori Sato * arch/sh/kernel/cpu/sh2a/clock-sh7206.c 39d4436a6SYoshinori Sato * 49d4436a6SYoshinori Sato * SH7206 support for the clock framework 59d4436a6SYoshinori Sato * 69d4436a6SYoshinori Sato * Copyright (C) 2006 Yoshinori Sato 79d4436a6SYoshinori Sato * 89d4436a6SYoshinori Sato * Based on clock-sh4.c 99d4436a6SYoshinori Sato * Copyright (C) 2005 Paul Mundt 109d4436a6SYoshinori Sato * 119d4436a6SYoshinori Sato * This file is subject to the terms and conditions of the GNU General Public 129d4436a6SYoshinori Sato * License. See the file "COPYING" in the main directory of this archive 139d4436a6SYoshinori Sato * for more details. 149d4436a6SYoshinori Sato */ 159d4436a6SYoshinori Sato #include <linux/init.h> 169d4436a6SYoshinori Sato #include <linux/kernel.h> 179d4436a6SYoshinori Sato #include <asm/clock.h> 189d4436a6SYoshinori Sato #include <asm/freq.h> 199d4436a6SYoshinori Sato #include <asm/io.h> 209d4436a6SYoshinori Sato 219d4436a6SYoshinori Sato const static int pll1rate[]={1,2,3,4,6,8}; 229d4436a6SYoshinori Sato const static int pfc_divisors[]={1,2,3,4,6,8,12}; 239d4436a6SYoshinori Sato #define ifc_divisors pfc_divisors 249d4436a6SYoshinori Sato 259d4436a6SYoshinori Sato #if (CONFIG_SH_CLK_MD == 2) 269d4436a6SYoshinori Sato #define PLL2 (4) 279d4436a6SYoshinori Sato #elif (CONFIG_SH_CLK_MD == 6) 289d4436a6SYoshinori Sato #define PLL2 (2) 299d4436a6SYoshinori Sato #elif (CONFIG_SH_CLK_MD == 7) 309d4436a6SYoshinori Sato #define PLL2 (1) 319d4436a6SYoshinori Sato #else 329d4436a6SYoshinori Sato #error "Illigal Clock Mode!" 339d4436a6SYoshinori Sato #endif 349d4436a6SYoshinori Sato 359d4436a6SYoshinori Sato static void master_clk_init(struct clk *clk) 369d4436a6SYoshinori Sato { 379d4436a6SYoshinori Sato clk->rate *= PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; 389d4436a6SYoshinori Sato } 399d4436a6SYoshinori Sato 409d4436a6SYoshinori Sato static struct clk_ops sh7206_master_clk_ops = { 419d4436a6SYoshinori Sato .init = master_clk_init, 429d4436a6SYoshinori Sato }; 439d4436a6SYoshinori Sato 449d4436a6SYoshinori Sato static void module_clk_recalc(struct clk *clk) 459d4436a6SYoshinori Sato { 469d4436a6SYoshinori Sato int idx = (ctrl_inw(FREQCR) & 0x0007); 479d4436a6SYoshinori Sato clk->rate = clk->parent->rate / pfc_divisors[idx]; 489d4436a6SYoshinori Sato } 499d4436a6SYoshinori Sato 509d4436a6SYoshinori Sato static struct clk_ops sh7206_module_clk_ops = { 519d4436a6SYoshinori Sato .recalc = module_clk_recalc, 529d4436a6SYoshinori Sato }; 539d4436a6SYoshinori Sato 549d4436a6SYoshinori Sato static void bus_clk_recalc(struct clk *clk) 559d4436a6SYoshinori Sato { 569d4436a6SYoshinori Sato clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; 579d4436a6SYoshinori Sato } 589d4436a6SYoshinori Sato 599d4436a6SYoshinori Sato static struct clk_ops sh7206_bus_clk_ops = { 609d4436a6SYoshinori Sato .recalc = bus_clk_recalc, 619d4436a6SYoshinori Sato }; 629d4436a6SYoshinori Sato 639d4436a6SYoshinori Sato static void cpu_clk_recalc(struct clk *clk) 649d4436a6SYoshinori Sato { 659d4436a6SYoshinori Sato int idx = (ctrl_inw(FREQCR) & 0x0007); 669d4436a6SYoshinori Sato clk->rate = clk->parent->rate / ifc_divisors[idx]; 679d4436a6SYoshinori Sato } 689d4436a6SYoshinori Sato 699d4436a6SYoshinori Sato static struct clk_ops sh7206_cpu_clk_ops = { 709d4436a6SYoshinori Sato .recalc = cpu_clk_recalc, 719d4436a6SYoshinori Sato }; 729d4436a6SYoshinori Sato 739d4436a6SYoshinori Sato static struct clk_ops *sh7206_clk_ops[] = { 749d4436a6SYoshinori Sato &sh7206_master_clk_ops, 759d4436a6SYoshinori Sato &sh7206_module_clk_ops, 769d4436a6SYoshinori Sato &sh7206_bus_clk_ops, 779d4436a6SYoshinori Sato &sh7206_cpu_clk_ops, 789d4436a6SYoshinori Sato }; 799d4436a6SYoshinori Sato 809d4436a6SYoshinori Sato void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 819d4436a6SYoshinori Sato { 829d4436a6SYoshinori Sato if (idx < ARRAY_SIZE(sh7206_clk_ops)) 839d4436a6SYoshinori Sato *ops = sh7206_clk_ops[idx]; 849d4436a6SYoshinori Sato } 859d4436a6SYoshinori Sato 86