19d4436a6SYoshinori Sato /* 29d4436a6SYoshinori Sato * arch/sh/kernel/cpu/sh2a/clock-sh7206.c 39d4436a6SYoshinori Sato * 49d4436a6SYoshinori Sato * SH7206 support for the clock framework 59d4436a6SYoshinori Sato * 69d4436a6SYoshinori Sato * Copyright (C) 2006 Yoshinori Sato 79d4436a6SYoshinori Sato * 89d4436a6SYoshinori Sato * Based on clock-sh4.c 99d4436a6SYoshinori Sato * Copyright (C) 2005 Paul Mundt 109d4436a6SYoshinori Sato * 119d4436a6SYoshinori Sato * This file is subject to the terms and conditions of the GNU General Public 129d4436a6SYoshinori Sato * License. See the file "COPYING" in the main directory of this archive 139d4436a6SYoshinori Sato * for more details. 149d4436a6SYoshinori Sato */ 159d4436a6SYoshinori Sato #include <linux/init.h> 169d4436a6SYoshinori Sato #include <linux/kernel.h> 179d4436a6SYoshinori Sato #include <asm/clock.h> 189d4436a6SYoshinori Sato #include <asm/freq.h> 199d4436a6SYoshinori Sato #include <asm/io.h> 209d4436a6SYoshinori Sato 21c5a69d57STobias Klauser static const int pll1rate[]={1,2,3,4,6,8}; 22c5a69d57STobias Klauser static const int pfc_divisors[]={1,2,3,4,6,8,12}; 239d4436a6SYoshinori Sato #define ifc_divisors pfc_divisors 249d4436a6SYoshinori Sato 2516b25920SPaul Mundt static unsigned int pll2_mult; 269d4436a6SYoshinori Sato 279d4436a6SYoshinori Sato static void master_clk_init(struct clk *clk) 289d4436a6SYoshinori Sato { 2916b25920SPaul Mundt clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; 309d4436a6SYoshinori Sato } 319d4436a6SYoshinori Sato 329d4436a6SYoshinori Sato static struct clk_ops sh7206_master_clk_ops = { 339d4436a6SYoshinori Sato .init = master_clk_init, 349d4436a6SYoshinori Sato }; 359d4436a6SYoshinori Sato 36b68d8201SPaul Mundt static unsigned long module_clk_recalc(struct clk *clk) 379d4436a6SYoshinori Sato { 389d56dd3bSPaul Mundt int idx = (__raw_readw(FREQCR) & 0x0007); 39b68d8201SPaul Mundt return clk->parent->rate / pfc_divisors[idx]; 409d4436a6SYoshinori Sato } 419d4436a6SYoshinori Sato 429d4436a6SYoshinori Sato static struct clk_ops sh7206_module_clk_ops = { 439d4436a6SYoshinori Sato .recalc = module_clk_recalc, 449d4436a6SYoshinori Sato }; 459d4436a6SYoshinori Sato 46b68d8201SPaul Mundt static unsigned long bus_clk_recalc(struct clk *clk) 479d4436a6SYoshinori Sato { 489d56dd3bSPaul Mundt return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; 499d4436a6SYoshinori Sato } 509d4436a6SYoshinori Sato 519d4436a6SYoshinori Sato static struct clk_ops sh7206_bus_clk_ops = { 529d4436a6SYoshinori Sato .recalc = bus_clk_recalc, 539d4436a6SYoshinori Sato }; 549d4436a6SYoshinori Sato 55b68d8201SPaul Mundt static unsigned long cpu_clk_recalc(struct clk *clk) 569d4436a6SYoshinori Sato { 579d56dd3bSPaul Mundt int idx = (__raw_readw(FREQCR) & 0x0007); 58b68d8201SPaul Mundt return clk->parent->rate / ifc_divisors[idx]; 599d4436a6SYoshinori Sato } 609d4436a6SYoshinori Sato 619d4436a6SYoshinori Sato static struct clk_ops sh7206_cpu_clk_ops = { 629d4436a6SYoshinori Sato .recalc = cpu_clk_recalc, 639d4436a6SYoshinori Sato }; 649d4436a6SYoshinori Sato 659d4436a6SYoshinori Sato static struct clk_ops *sh7206_clk_ops[] = { 669d4436a6SYoshinori Sato &sh7206_master_clk_ops, 679d4436a6SYoshinori Sato &sh7206_module_clk_ops, 689d4436a6SYoshinori Sato &sh7206_bus_clk_ops, 699d4436a6SYoshinori Sato &sh7206_cpu_clk_ops, 709d4436a6SYoshinori Sato }; 719d4436a6SYoshinori Sato 729d4436a6SYoshinori Sato void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 739d4436a6SYoshinori Sato { 7416b25920SPaul Mundt if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0)) 7516b25920SPaul Mundt pll2_mult = 1; 7616b25920SPaul Mundt else if (test_mode_pin(MODE_PIN2 | MODE_PIN1)) 7716b25920SPaul Mundt pll2_mult = 2; 7816b25920SPaul Mundt else if (test_mode_pin(MODE_PIN1)) 7916b25920SPaul Mundt pll2_mult = 4; 8016b25920SPaul Mundt 819d4436a6SYoshinori Sato if (idx < ARRAY_SIZE(sh7206_clk_ops)) 829d4436a6SYoshinori Sato *ops = sh7206_clk_ops[idx]; 839d4436a6SYoshinori Sato } 84