1 /* 2 * arch/sh/kernel/cpu/init.c 3 * 4 * CPU init code 5 * 6 * Copyright (C) 2002 - 2009 Paul Mundt 7 * Copyright (C) 2003 Richard Curnow 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/log2.h> 17 #include <asm/mmu_context.h> 18 #include <asm/processor.h> 19 #include <asm/uaccess.h> 20 #include <asm/page.h> 21 #include <asm/system.h> 22 #include <asm/cacheflush.h> 23 #include <asm/cache.h> 24 #include <asm/elf.h> 25 #include <asm/io.h> 26 #include <asm/smp.h> 27 #ifdef CONFIG_SUPERH32 28 #include <asm/ubc.h> 29 #endif 30 31 /* 32 * Generic wrapper for command line arguments to disable on-chip 33 * peripherals (nofpu, nodsp, and so forth). 34 */ 35 #define onchip_setup(x) \ 36 static int x##_disabled __initdata = 0; \ 37 \ 38 static int __init x##_setup(char *opts) \ 39 { \ 40 x##_disabled = 1; \ 41 return 1; \ 42 } \ 43 __setup("no" __stringify(x), x##_setup); 44 45 onchip_setup(fpu); 46 onchip_setup(dsp); 47 48 #ifdef CONFIG_SPECULATIVE_EXECUTION 49 #define CPUOPM 0xff2f0000 50 #define CPUOPM_RABD (1 << 5) 51 52 static void __init speculative_execution_init(void) 53 { 54 /* Clear RABD */ 55 ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); 56 57 /* Flush the update */ 58 (void)ctrl_inl(CPUOPM); 59 ctrl_barrier(); 60 } 61 #else 62 #define speculative_execution_init() do { } while (0) 63 #endif 64 65 #ifdef CONFIG_CPU_SH4A 66 #define EXPMASK 0xff2f0004 67 #define EXPMASK_RTEDS (1 << 0) 68 #define EXPMASK_BRDSSLP (1 << 1) 69 #define EXPMASK_MMCAW (1 << 4) 70 71 static void __init expmask_init(void) 72 { 73 unsigned long expmask = __raw_readl(EXPMASK); 74 75 /* 76 * Future proofing. 77 * 78 * Disable support for slottable sleep instruction, non-nop 79 * instructions in the rte delay slot, and associative writes to 80 * the memory-mapped cache array. 81 */ 82 expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP | EXPMASK_MMCAW); 83 84 __raw_writel(expmask, EXPMASK); 85 ctrl_barrier(); 86 } 87 #else 88 #define expmask_init() do { } while (0) 89 #endif 90 91 /* 2nd-level cache init */ 92 void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void) 93 { 94 } 95 96 /* 97 * Generic first-level cache init 98 */ 99 #ifdef CONFIG_SUPERH32 100 static void __uses_jump_to_uncached cache_init(void) 101 { 102 unsigned long ccr, flags; 103 104 jump_to_uncached(); 105 ccr = ctrl_inl(CCR); 106 107 /* 108 * At this point we don't know whether the cache is enabled or not - a 109 * bootloader may have enabled it. There are at least 2 things that 110 * could be dirty in the cache at this point: 111 * 1. kernel command line set up by boot loader 112 * 2. spilled registers from the prolog of this function 113 * => before re-initialising the cache, we must do a purge of the whole 114 * cache out to memory for safety. As long as nothing is spilled 115 * during the loop to lines that have already been done, this is safe. 116 * - RPC 117 */ 118 if (ccr & CCR_CACHE_ENABLE) { 119 unsigned long ways, waysize, addrstart; 120 121 waysize = current_cpu_data.dcache.sets; 122 123 #ifdef CCR_CACHE_ORA 124 /* 125 * If the OC is already in RAM mode, we only have 126 * half of the entries to flush.. 127 */ 128 if (ccr & CCR_CACHE_ORA) 129 waysize >>= 1; 130 #endif 131 132 waysize <<= current_cpu_data.dcache.entry_shift; 133 134 #ifdef CCR_CACHE_EMODE 135 /* If EMODE is not set, we only have 1 way to flush. */ 136 if (!(ccr & CCR_CACHE_EMODE)) 137 ways = 1; 138 else 139 #endif 140 ways = current_cpu_data.dcache.ways; 141 142 addrstart = CACHE_OC_ADDRESS_ARRAY; 143 do { 144 unsigned long addr; 145 146 for (addr = addrstart; 147 addr < addrstart + waysize; 148 addr += current_cpu_data.dcache.linesz) 149 ctrl_outl(0, addr); 150 151 addrstart += current_cpu_data.dcache.way_incr; 152 } while (--ways); 153 } 154 155 /* 156 * Default CCR values .. enable the caches 157 * and invalidate them immediately.. 158 */ 159 flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE; 160 161 #ifdef CCR_CACHE_EMODE 162 /* Force EMODE if possible */ 163 if (current_cpu_data.dcache.ways > 1) 164 flags |= CCR_CACHE_EMODE; 165 else 166 flags &= ~CCR_CACHE_EMODE; 167 #endif 168 169 #if defined(CONFIG_CACHE_WRITETHROUGH) 170 /* Write-through */ 171 flags |= CCR_CACHE_WT; 172 #elif defined(CONFIG_CACHE_WRITEBACK) 173 /* Write-back */ 174 flags |= CCR_CACHE_CB; 175 #else 176 /* Off */ 177 flags &= ~CCR_CACHE_ENABLE; 178 #endif 179 180 l2_cache_init(); 181 182 ctrl_outl(flags, CCR); 183 back_to_cached(); 184 } 185 #else 186 #define cache_init() do { } while (0) 187 #endif 188 189 #define CSHAPE(totalsize, linesize, assoc) \ 190 ((totalsize & ~0xff) | (linesize << 4) | assoc) 191 192 #define CACHE_DESC_SHAPE(desc) \ 193 CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways) 194 195 static void detect_cache_shape(void) 196 { 197 l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache); 198 199 if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED) 200 l1i_cache_shape = l1d_cache_shape; 201 else 202 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache); 203 204 if (current_cpu_data.flags & CPU_HAS_L2_CACHE) 205 l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache); 206 else 207 l2_cache_shape = -1; /* No S-cache */ 208 } 209 210 #ifdef CONFIG_SH_DSP 211 static void __init release_dsp(void) 212 { 213 unsigned long sr; 214 215 /* Clear SR.DSP bit */ 216 __asm__ __volatile__ ( 217 "stc\tsr, %0\n\t" 218 "and\t%1, %0\n\t" 219 "ldc\t%0, sr\n\t" 220 : "=&r" (sr) 221 : "r" (~SR_DSP) 222 ); 223 } 224 225 static void __init dsp_init(void) 226 { 227 unsigned long sr; 228 229 /* 230 * Set the SR.DSP bit, wait for one instruction, and then read 231 * back the SR value. 232 */ 233 __asm__ __volatile__ ( 234 "stc\tsr, %0\n\t" 235 "or\t%1, %0\n\t" 236 "ldc\t%0, sr\n\t" 237 "nop\n\t" 238 "stc\tsr, %0\n\t" 239 : "=&r" (sr) 240 : "r" (SR_DSP) 241 ); 242 243 /* If the DSP bit is still set, this CPU has a DSP */ 244 if (sr & SR_DSP) 245 current_cpu_data.flags |= CPU_HAS_DSP; 246 247 /* Now that we've determined the DSP status, clear the DSP bit. */ 248 release_dsp(); 249 } 250 #endif /* CONFIG_SH_DSP */ 251 252 /** 253 * sh_cpu_init 254 * 255 * This is our initial entry point for each CPU, and is invoked on the boot 256 * CPU prior to calling start_kernel(). For SMP, a combination of this and 257 * start_secondary() will bring up each processor to a ready state prior 258 * to hand forking the idle loop. 259 * 260 * We do all of the basic processor init here, including setting up the 261 * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is 262 * hit (and subsequently platform_setup()) things like determining the 263 * CPU subtype and initial configuration will all be done. 264 * 265 * Each processor family is still responsible for doing its own probing 266 * and cache configuration in detect_cpu_and_cache_system(). 267 */ 268 269 asmlinkage void __init sh_cpu_init(void) 270 { 271 current_thread_info()->cpu = hard_smp_processor_id(); 272 273 /* First, probe the CPU */ 274 detect_cpu_and_cache_system(); 275 276 if (current_cpu_data.type == CPU_SH_NONE) 277 panic("Unknown CPU"); 278 279 /* First setup the rest of the I-cache info */ 280 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - 281 current_cpu_data.icache.linesz; 282 283 current_cpu_data.icache.way_size = current_cpu_data.icache.sets * 284 current_cpu_data.icache.linesz; 285 286 /* And the D-cache too */ 287 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - 288 current_cpu_data.dcache.linesz; 289 290 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * 291 current_cpu_data.dcache.linesz; 292 293 /* Init the cache */ 294 cache_init(); 295 296 if (raw_smp_processor_id() == 0) { 297 shm_align_mask = max_t(unsigned long, 298 current_cpu_data.dcache.way_size - 1, 299 PAGE_SIZE - 1); 300 301 /* Boot CPU sets the cache shape */ 302 detect_cache_shape(); 303 } 304 305 /* Disable the FPU */ 306 if (fpu_disabled) { 307 printk("FPU Disabled\n"); 308 current_cpu_data.flags &= ~CPU_HAS_FPU; 309 } 310 311 /* FPU initialization */ 312 disable_fpu(); 313 if ((current_cpu_data.flags & CPU_HAS_FPU)) { 314 current_thread_info()->status &= ~TS_USEDFPU; 315 clear_used_math(); 316 } 317 318 /* 319 * Initialize the per-CPU ASID cache very early, since the 320 * TLB flushing routines depend on this being setup. 321 */ 322 current_cpu_data.asid_cache = NO_CONTEXT; 323 324 #ifdef CONFIG_SH_DSP 325 /* Probe for DSP */ 326 dsp_init(); 327 328 /* Disable the DSP */ 329 if (dsp_disabled) { 330 printk("DSP Disabled\n"); 331 current_cpu_data.flags &= ~CPU_HAS_DSP; 332 release_dsp(); 333 } 334 #endif 335 336 speculative_execution_init(); 337 expmask_init(); 338 } 339