1 /* 2 * arch/sh/kernel/cpu/init.c 3 * 4 * CPU init code 5 * 6 * Copyright (C) 2002 - 2009 Paul Mundt 7 * Copyright (C) 2003 Richard Curnow 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/log2.h> 17 #include <asm/mmu_context.h> 18 #include <asm/processor.h> 19 #include <asm/uaccess.h> 20 #include <asm/page.h> 21 #include <asm/system.h> 22 #include <asm/cacheflush.h> 23 #include <asm/cache.h> 24 #include <asm/elf.h> 25 #include <asm/io.h> 26 #include <asm/smp.h> 27 28 #ifdef CONFIG_SH_FPU 29 #define cpu_has_fpu 1 30 #else 31 #define cpu_has_fpu 0 32 #endif 33 34 #ifdef CONFIG_SH_DSP 35 #define cpu_has_dsp 1 36 #else 37 #define cpu_has_dsp 0 38 #endif 39 40 /* 41 * Generic wrapper for command line arguments to disable on-chip 42 * peripherals (nofpu, nodsp, and so forth). 43 */ 44 #define onchip_setup(x) \ 45 static int x##_disabled __initdata = !cpu_has_##x; \ 46 \ 47 static int __init x##_setup(char *opts) \ 48 { \ 49 x##_disabled = 1; \ 50 return 1; \ 51 } \ 52 __setup("no" __stringify(x), x##_setup); 53 54 onchip_setup(fpu); 55 onchip_setup(dsp); 56 57 #ifdef CONFIG_SPECULATIVE_EXECUTION 58 #define CPUOPM 0xff2f0000 59 #define CPUOPM_RABD (1 << 5) 60 61 static void __init speculative_execution_init(void) 62 { 63 /* Clear RABD */ 64 ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); 65 66 /* Flush the update */ 67 (void)ctrl_inl(CPUOPM); 68 ctrl_barrier(); 69 } 70 #else 71 #define speculative_execution_init() do { } while (0) 72 #endif 73 74 #ifdef CONFIG_CPU_SH4A 75 #define EXPMASK 0xff2f0004 76 #define EXPMASK_RTEDS (1 << 0) 77 #define EXPMASK_BRDSSLP (1 << 1) 78 #define EXPMASK_MMCAW (1 << 4) 79 80 static void __init expmask_init(void) 81 { 82 unsigned long expmask = __raw_readl(EXPMASK); 83 84 /* 85 * Future proofing. 86 * 87 * Disable support for slottable sleep instruction, non-nop 88 * instructions in the rte delay slot, and associative writes to 89 * the memory-mapped cache array. 90 */ 91 expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP | EXPMASK_MMCAW); 92 93 __raw_writel(expmask, EXPMASK); 94 ctrl_barrier(); 95 } 96 #else 97 #define expmask_init() do { } while (0) 98 #endif 99 100 /* 2nd-level cache init */ 101 void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void) 102 { 103 } 104 105 /* 106 * Generic first-level cache init 107 */ 108 #ifdef CONFIG_SUPERH32 109 static void __uses_jump_to_uncached cache_init(void) 110 { 111 unsigned long ccr, flags; 112 113 jump_to_uncached(); 114 ccr = ctrl_inl(CCR); 115 116 /* 117 * At this point we don't know whether the cache is enabled or not - a 118 * bootloader may have enabled it. There are at least 2 things that 119 * could be dirty in the cache at this point: 120 * 1. kernel command line set up by boot loader 121 * 2. spilled registers from the prolog of this function 122 * => before re-initialising the cache, we must do a purge of the whole 123 * cache out to memory for safety. As long as nothing is spilled 124 * during the loop to lines that have already been done, this is safe. 125 * - RPC 126 */ 127 if (ccr & CCR_CACHE_ENABLE) { 128 unsigned long ways, waysize, addrstart; 129 130 waysize = current_cpu_data.dcache.sets; 131 132 #ifdef CCR_CACHE_ORA 133 /* 134 * If the OC is already in RAM mode, we only have 135 * half of the entries to flush.. 136 */ 137 if (ccr & CCR_CACHE_ORA) 138 waysize >>= 1; 139 #endif 140 141 waysize <<= current_cpu_data.dcache.entry_shift; 142 143 #ifdef CCR_CACHE_EMODE 144 /* If EMODE is not set, we only have 1 way to flush. */ 145 if (!(ccr & CCR_CACHE_EMODE)) 146 ways = 1; 147 else 148 #endif 149 ways = current_cpu_data.dcache.ways; 150 151 addrstart = CACHE_OC_ADDRESS_ARRAY; 152 do { 153 unsigned long addr; 154 155 for (addr = addrstart; 156 addr < addrstart + waysize; 157 addr += current_cpu_data.dcache.linesz) 158 ctrl_outl(0, addr); 159 160 addrstart += current_cpu_data.dcache.way_incr; 161 } while (--ways); 162 } 163 164 /* 165 * Default CCR values .. enable the caches 166 * and invalidate them immediately.. 167 */ 168 flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE; 169 170 #ifdef CCR_CACHE_EMODE 171 /* Force EMODE if possible */ 172 if (current_cpu_data.dcache.ways > 1) 173 flags |= CCR_CACHE_EMODE; 174 else 175 flags &= ~CCR_CACHE_EMODE; 176 #endif 177 178 #if defined(CONFIG_CACHE_WRITETHROUGH) 179 /* Write-through */ 180 flags |= CCR_CACHE_WT; 181 #elif defined(CONFIG_CACHE_WRITEBACK) 182 /* Write-back */ 183 flags |= CCR_CACHE_CB; 184 #else 185 /* Off */ 186 flags &= ~CCR_CACHE_ENABLE; 187 #endif 188 189 l2_cache_init(); 190 191 ctrl_outl(flags, CCR); 192 back_to_cached(); 193 } 194 #else 195 #define cache_init() do { } while (0) 196 #endif 197 198 #define CSHAPE(totalsize, linesize, assoc) \ 199 ((totalsize & ~0xff) | (linesize << 4) | assoc) 200 201 #define CACHE_DESC_SHAPE(desc) \ 202 CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways) 203 204 static void detect_cache_shape(void) 205 { 206 l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache); 207 208 if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED) 209 l1i_cache_shape = l1d_cache_shape; 210 else 211 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache); 212 213 if (current_cpu_data.flags & CPU_HAS_L2_CACHE) 214 l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache); 215 else 216 l2_cache_shape = -1; /* No S-cache */ 217 } 218 219 static void __init fpu_init(void) 220 { 221 /* Disable the FPU */ 222 if (fpu_disabled && (current_cpu_data.flags & CPU_HAS_FPU)) { 223 printk("FPU Disabled\n"); 224 current_cpu_data.flags &= ~CPU_HAS_FPU; 225 } 226 227 disable_fpu(); 228 clear_used_math(); 229 } 230 231 #ifdef CONFIG_SH_DSP 232 static void __init release_dsp(void) 233 { 234 unsigned long sr; 235 236 /* Clear SR.DSP bit */ 237 __asm__ __volatile__ ( 238 "stc\tsr, %0\n\t" 239 "and\t%1, %0\n\t" 240 "ldc\t%0, sr\n\t" 241 : "=&r" (sr) 242 : "r" (~SR_DSP) 243 ); 244 } 245 246 static void __init dsp_init(void) 247 { 248 unsigned long sr; 249 250 /* 251 * Set the SR.DSP bit, wait for one instruction, and then read 252 * back the SR value. 253 */ 254 __asm__ __volatile__ ( 255 "stc\tsr, %0\n\t" 256 "or\t%1, %0\n\t" 257 "ldc\t%0, sr\n\t" 258 "nop\n\t" 259 "stc\tsr, %0\n\t" 260 : "=&r" (sr) 261 : "r" (SR_DSP) 262 ); 263 264 /* If the DSP bit is still set, this CPU has a DSP */ 265 if (sr & SR_DSP) 266 current_cpu_data.flags |= CPU_HAS_DSP; 267 268 /* Disable the DSP */ 269 if (dsp_disabled && (current_cpu_data.flags & CPU_HAS_DSP)) { 270 printk("DSP Disabled\n"); 271 current_cpu_data.flags &= ~CPU_HAS_DSP; 272 } 273 274 /* Now that we've determined the DSP status, clear the DSP bit. */ 275 release_dsp(); 276 } 277 #else 278 static inline void __init dsp_init(void) { } 279 #endif /* CONFIG_SH_DSP */ 280 281 /** 282 * sh_cpu_init 283 * 284 * This is our initial entry point for each CPU, and is invoked on the 285 * boot CPU prior to calling start_kernel(). For SMP, a combination of 286 * this and start_secondary() will bring up each processor to a ready 287 * state prior to hand forking the idle loop. 288 * 289 * We do all of the basic processor init here, including setting up 290 * the caches, FPU, DSP, etc. By the time start_kernel() is hit (and 291 * subsequently platform_setup()) things like determining the CPU 292 * subtype and initial configuration will all be done. 293 * 294 * Each processor family is still responsible for doing its own probing 295 * and cache configuration in detect_cpu_and_cache_system(). 296 */ 297 asmlinkage void __init sh_cpu_init(void) 298 { 299 current_thread_info()->cpu = hard_smp_processor_id(); 300 301 /* First, probe the CPU */ 302 detect_cpu_and_cache_system(); 303 304 if (current_cpu_data.type == CPU_SH_NONE) 305 panic("Unknown CPU"); 306 307 /* First setup the rest of the I-cache info */ 308 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - 309 current_cpu_data.icache.linesz; 310 311 current_cpu_data.icache.way_size = current_cpu_data.icache.sets * 312 current_cpu_data.icache.linesz; 313 314 /* And the D-cache too */ 315 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - 316 current_cpu_data.dcache.linesz; 317 318 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * 319 current_cpu_data.dcache.linesz; 320 321 /* Init the cache */ 322 cache_init(); 323 324 if (raw_smp_processor_id() == 0) { 325 shm_align_mask = max_t(unsigned long, 326 current_cpu_data.dcache.way_size - 1, 327 PAGE_SIZE - 1); 328 329 /* Boot CPU sets the cache shape */ 330 detect_cache_shape(); 331 } 332 333 fpu_init(); 334 dsp_init(); 335 336 /* 337 * Initialize the per-CPU ASID cache very early, since the 338 * TLB flushing routines depend on this being setup. 339 */ 340 current_cpu_data.asid_cache = NO_CONTEXT; 341 342 speculative_execution_init(); 343 expmask_init(); 344 345 /* 346 * Boot processor to setup the FP and extended state context info. 347 */ 348 if (raw_smp_processor_id() == 0) 349 init_thread_xstate(); 350 } 351