1 /* 2 * arch/sh/kernel/cpu/init.c 3 * 4 * CPU init code 5 * 6 * Copyright (C) 2002 - 2007 Paul Mundt 7 * Copyright (C) 2003 Richard Curnow 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/log2.h> 17 #include <asm/mmu_context.h> 18 #include <asm/processor.h> 19 #include <asm/uaccess.h> 20 #include <asm/page.h> 21 #include <asm/system.h> 22 #include <asm/cacheflush.h> 23 #include <asm/cache.h> 24 #include <asm/elf.h> 25 #include <asm/io.h> 26 #include <asm/smp.h> 27 #ifdef CONFIG_SUPERH32 28 #include <asm/ubc.h> 29 #endif 30 31 /* 32 * Generic wrapper for command line arguments to disable on-chip 33 * peripherals (nofpu, nodsp, and so forth). 34 */ 35 #define onchip_setup(x) \ 36 static int x##_disabled __initdata = 0; \ 37 \ 38 static int __init x##_setup(char *opts) \ 39 { \ 40 x##_disabled = 1; \ 41 return 1; \ 42 } \ 43 __setup("no" __stringify(x), x##_setup); 44 45 onchip_setup(fpu); 46 onchip_setup(dsp); 47 48 #ifdef CONFIG_SPECULATIVE_EXECUTION 49 #define CPUOPM 0xff2f0000 50 #define CPUOPM_RABD (1 << 5) 51 52 static void __init speculative_execution_init(void) 53 { 54 /* Clear RABD */ 55 ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); 56 57 /* Flush the update */ 58 (void)ctrl_inl(CPUOPM); 59 ctrl_barrier(); 60 } 61 #else 62 #define speculative_execution_init() do { } while (0) 63 #endif 64 65 /* 2nd-level cache init */ 66 void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void) 67 { 68 } 69 70 /* 71 * Generic first-level cache init 72 */ 73 #ifdef CONFIG_SUPERH32 74 static void __uses_jump_to_uncached cache_init(void) 75 { 76 unsigned long ccr, flags; 77 78 jump_to_uncached(); 79 ccr = ctrl_inl(CCR); 80 81 /* 82 * At this point we don't know whether the cache is enabled or not - a 83 * bootloader may have enabled it. There are at least 2 things that 84 * could be dirty in the cache at this point: 85 * 1. kernel command line set up by boot loader 86 * 2. spilled registers from the prolog of this function 87 * => before re-initialising the cache, we must do a purge of the whole 88 * cache out to memory for safety. As long as nothing is spilled 89 * during the loop to lines that have already been done, this is safe. 90 * - RPC 91 */ 92 if (ccr & CCR_CACHE_ENABLE) { 93 unsigned long ways, waysize, addrstart; 94 95 waysize = current_cpu_data.dcache.sets; 96 97 #ifdef CCR_CACHE_ORA 98 /* 99 * If the OC is already in RAM mode, we only have 100 * half of the entries to flush.. 101 */ 102 if (ccr & CCR_CACHE_ORA) 103 waysize >>= 1; 104 #endif 105 106 waysize <<= current_cpu_data.dcache.entry_shift; 107 108 #ifdef CCR_CACHE_EMODE 109 /* If EMODE is not set, we only have 1 way to flush. */ 110 if (!(ccr & CCR_CACHE_EMODE)) 111 ways = 1; 112 else 113 #endif 114 ways = current_cpu_data.dcache.ways; 115 116 addrstart = CACHE_OC_ADDRESS_ARRAY; 117 do { 118 unsigned long addr; 119 120 for (addr = addrstart; 121 addr < addrstart + waysize; 122 addr += current_cpu_data.dcache.linesz) 123 ctrl_outl(0, addr); 124 125 addrstart += current_cpu_data.dcache.way_incr; 126 } while (--ways); 127 } 128 129 /* 130 * Default CCR values .. enable the caches 131 * and invalidate them immediately.. 132 */ 133 flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE; 134 135 #ifdef CCR_CACHE_EMODE 136 /* Force EMODE if possible */ 137 if (current_cpu_data.dcache.ways > 1) 138 flags |= CCR_CACHE_EMODE; 139 else 140 flags &= ~CCR_CACHE_EMODE; 141 #endif 142 143 #if defined(CONFIG_CACHE_WRITETHROUGH) 144 /* Write-through */ 145 flags |= CCR_CACHE_WT; 146 #elif defined(CONFIG_CACHE_WRITEBACK) 147 /* Write-back */ 148 flags |= CCR_CACHE_CB; 149 #else 150 /* Off */ 151 flags &= ~CCR_CACHE_ENABLE; 152 #endif 153 154 l2_cache_init(); 155 156 ctrl_outl(flags, CCR); 157 back_to_cached(); 158 } 159 #else 160 #define cache_init() do { } while (0) 161 #endif 162 163 #define CSHAPE(totalsize, linesize, assoc) \ 164 ((totalsize & ~0xff) | (linesize << 4) | assoc) 165 166 #define CACHE_DESC_SHAPE(desc) \ 167 CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways) 168 169 static void detect_cache_shape(void) 170 { 171 l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache); 172 173 if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED) 174 l1i_cache_shape = l1d_cache_shape; 175 else 176 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache); 177 178 if (current_cpu_data.flags & CPU_HAS_L2_CACHE) 179 l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache); 180 else 181 l2_cache_shape = -1; /* No S-cache */ 182 } 183 184 #ifdef CONFIG_SH_DSP 185 static void __init release_dsp(void) 186 { 187 unsigned long sr; 188 189 /* Clear SR.DSP bit */ 190 __asm__ __volatile__ ( 191 "stc\tsr, %0\n\t" 192 "and\t%1, %0\n\t" 193 "ldc\t%0, sr\n\t" 194 : "=&r" (sr) 195 : "r" (~SR_DSP) 196 ); 197 } 198 199 static void __init dsp_init(void) 200 { 201 unsigned long sr; 202 203 /* 204 * Set the SR.DSP bit, wait for one instruction, and then read 205 * back the SR value. 206 */ 207 __asm__ __volatile__ ( 208 "stc\tsr, %0\n\t" 209 "or\t%1, %0\n\t" 210 "ldc\t%0, sr\n\t" 211 "nop\n\t" 212 "stc\tsr, %0\n\t" 213 : "=&r" (sr) 214 : "r" (SR_DSP) 215 ); 216 217 /* If the DSP bit is still set, this CPU has a DSP */ 218 if (sr & SR_DSP) 219 current_cpu_data.flags |= CPU_HAS_DSP; 220 221 /* Now that we've determined the DSP status, clear the DSP bit. */ 222 release_dsp(); 223 } 224 #endif /* CONFIG_SH_DSP */ 225 226 /** 227 * sh_cpu_init 228 * 229 * This is our initial entry point for each CPU, and is invoked on the boot 230 * CPU prior to calling start_kernel(). For SMP, a combination of this and 231 * start_secondary() will bring up each processor to a ready state prior 232 * to hand forking the idle loop. 233 * 234 * We do all of the basic processor init here, including setting up the 235 * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is 236 * hit (and subsequently platform_setup()) things like determining the 237 * CPU subtype and initial configuration will all be done. 238 * 239 * Each processor family is still responsible for doing its own probing 240 * and cache configuration in detect_cpu_and_cache_system(). 241 */ 242 243 asmlinkage void __init sh_cpu_init(void) 244 { 245 current_thread_info()->cpu = hard_smp_processor_id(); 246 247 /* First, probe the CPU */ 248 detect_cpu_and_cache_system(); 249 250 if (current_cpu_data.type == CPU_SH_NONE) 251 panic("Unknown CPU"); 252 253 /* First setup the rest of the I-cache info */ 254 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - 255 current_cpu_data.icache.linesz; 256 257 current_cpu_data.icache.way_size = current_cpu_data.icache.sets * 258 current_cpu_data.icache.linesz; 259 260 /* And the D-cache too */ 261 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - 262 current_cpu_data.dcache.linesz; 263 264 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * 265 current_cpu_data.dcache.linesz; 266 267 /* Init the cache */ 268 cache_init(); 269 270 if (raw_smp_processor_id() == 0) { 271 #ifdef CONFIG_MMU 272 shm_align_mask = max_t(unsigned long, 273 current_cpu_data.dcache.way_size - 1, 274 PAGE_SIZE - 1); 275 #endif 276 277 /* Boot CPU sets the cache shape */ 278 detect_cache_shape(); 279 } 280 281 /* Disable the FPU */ 282 if (fpu_disabled) { 283 printk("FPU Disabled\n"); 284 current_cpu_data.flags &= ~CPU_HAS_FPU; 285 disable_fpu(); 286 } 287 288 /* FPU initialization */ 289 if ((current_cpu_data.flags & CPU_HAS_FPU)) { 290 clear_thread_flag(TIF_USEDFPU); 291 clear_used_math(); 292 } 293 294 /* 295 * Initialize the per-CPU ASID cache very early, since the 296 * TLB flushing routines depend on this being setup. 297 */ 298 current_cpu_data.asid_cache = NO_CONTEXT; 299 300 #ifdef CONFIG_SH_DSP 301 /* Probe for DSP */ 302 dsp_init(); 303 304 /* Disable the DSP */ 305 if (dsp_disabled) { 306 printk("DSP Disabled\n"); 307 current_cpu_data.flags &= ~CPU_HAS_DSP; 308 release_dsp(); 309 } 310 #endif 311 312 /* 313 * Some brain-damaged loaders decided it would be a good idea to put 314 * the UBC to sleep. This causes some issues when it comes to things 315 * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So .. 316 * we wake it up and hope that all is well. 317 */ 318 #ifdef CONFIG_SUPERH32 319 if (raw_smp_processor_id() == 0) 320 ubc_wakeup(); 321 #endif 322 323 speculative_execution_init(); 324 } 325