xref: /openbmc/linux/arch/sh/kernel/cpu/clock.c (revision 64c70b1c) 
1 /*
2  * arch/sh/kernel/cpu/clock.c - SuperH clock framework
3  *
4  *  Copyright (C) 2005, 2006, 2007  Paul Mundt
5  *
6  * This clock framework is derived from the OMAP version by:
7  *
8  *	Copyright (C) 2004 - 2005 Nokia Corporation
9  *	Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10  *
11  *  Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
12  *
13  * This file is subject to the terms and conditions of the GNU General Public
14  * License.  See the file "COPYING" in the main directory of this archive
15  * for more details.
16  */
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/mutex.h>
21 #include <linux/list.h>
22 #include <linux/kref.h>
23 #include <linux/seq_file.h>
24 #include <linux/err.h>
25 #include <linux/platform_device.h>
26 #include <linux/proc_fs.h>
27 #include <asm/clock.h>
28 #include <asm/timer.h>
29 
30 static LIST_HEAD(clock_list);
31 static DEFINE_SPINLOCK(clock_lock);
32 static DEFINE_MUTEX(clock_list_sem);
33 
34 /*
35  * Each subtype is expected to define the init routines for these clocks,
36  * as each subtype (or processor family) will have these clocks at the
37  * very least. These are all provided through the CPG, which even some of
38  * the more quirky parts (such as ST40, SH4-202, etc.) still have.
39  *
40  * The processor-specific code is expected to register any additional
41  * clock sources that are of interest.
42  */
43 static struct clk master_clk = {
44 	.name		= "master_clk",
45 	.flags		= CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
46 	.rate		= CONFIG_SH_PCLK_FREQ,
47 };
48 
49 static struct clk module_clk = {
50 	.name		= "module_clk",
51 	.parent		= &master_clk,
52 	.flags		= CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
53 };
54 
55 static struct clk bus_clk = {
56 	.name		= "bus_clk",
57 	.parent		= &master_clk,
58 	.flags		= CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
59 };
60 
61 static struct clk cpu_clk = {
62 	.name		= "cpu_clk",
63 	.parent		= &master_clk,
64 	.flags		= CLK_ALWAYS_ENABLED,
65 };
66 
67 /*
68  * The ordering of these clocks matters, do not change it.
69  */
70 static struct clk *onchip_clocks[] = {
71 	&master_clk,
72 	&module_clk,
73 	&bus_clk,
74 	&cpu_clk,
75 };
76 
77 static void propagate_rate(struct clk *clk)
78 {
79 	struct clk *clkp;
80 
81 	list_for_each_entry(clkp, &clock_list, node) {
82 		if (likely(clkp->parent != clk))
83 			continue;
84 		if (likely(clkp->ops && clkp->ops->recalc))
85 			clkp->ops->recalc(clkp);
86 	}
87 }
88 
89 int __clk_enable(struct clk *clk)
90 {
91 	/*
92 	 * See if this is the first time we're enabling the clock, some
93 	 * clocks that are always enabled still require "special"
94 	 * initialization. This is especially true if the clock mode
95 	 * changes and the clock needs to hunt for the proper set of
96 	 * divisors to use before it can effectively recalc.
97 	 */
98 	if (unlikely(atomic_read(&clk->kref.refcount) == 1))
99 		if (clk->ops && clk->ops->init)
100 			clk->ops->init(clk);
101 
102 	kref_get(&clk->kref);
103 
104 	if (clk->flags & CLK_ALWAYS_ENABLED)
105 		return 0;
106 
107 	if (likely(clk->ops && clk->ops->enable))
108 		clk->ops->enable(clk);
109 
110 	return 0;
111 }
112 EXPORT_SYMBOL_GPL(__clk_enable);
113 
114 int clk_enable(struct clk *clk)
115 {
116 	unsigned long flags;
117 	int ret;
118 
119 	spin_lock_irqsave(&clock_lock, flags);
120 	ret = __clk_enable(clk);
121 	spin_unlock_irqrestore(&clock_lock, flags);
122 
123 	return ret;
124 }
125 EXPORT_SYMBOL_GPL(clk_enable);
126 
127 static void clk_kref_release(struct kref *kref)
128 {
129 	/* Nothing to do */
130 }
131 
132 void __clk_disable(struct clk *clk)
133 {
134 	int count = kref_put(&clk->kref, clk_kref_release);
135 
136 	if (clk->flags & CLK_ALWAYS_ENABLED)
137 		return;
138 
139 	if (!count) {	/* count reaches zero, disable the clock */
140 		if (likely(clk->ops && clk->ops->disable))
141 			clk->ops->disable(clk);
142 	}
143 }
144 EXPORT_SYMBOL_GPL(__clk_disable);
145 
146 void clk_disable(struct clk *clk)
147 {
148 	unsigned long flags;
149 
150 	spin_lock_irqsave(&clock_lock, flags);
151 	__clk_disable(clk);
152 	spin_unlock_irqrestore(&clock_lock, flags);
153 }
154 EXPORT_SYMBOL_GPL(clk_disable);
155 
156 int clk_register(struct clk *clk)
157 {
158 	mutex_lock(&clock_list_sem);
159 
160 	list_add(&clk->node, &clock_list);
161 	kref_init(&clk->kref);
162 
163 	mutex_unlock(&clock_list_sem);
164 
165 	if (clk->flags & CLK_ALWAYS_ENABLED) {
166 		pr_debug( "Clock '%s' is ALWAYS_ENABLED\n", clk->name);
167 		if (clk->ops && clk->ops->init)
168 			clk->ops->init(clk);
169 		if (clk->ops && clk->ops->enable)
170 			clk->ops->enable(clk);
171 		pr_debug( "Enabled.");
172 	}
173 
174 	return 0;
175 }
176 EXPORT_SYMBOL_GPL(clk_register);
177 
178 void clk_unregister(struct clk *clk)
179 {
180 	mutex_lock(&clock_list_sem);
181 	list_del(&clk->node);
182 	mutex_unlock(&clock_list_sem);
183 }
184 EXPORT_SYMBOL_GPL(clk_unregister);
185 
186 unsigned long clk_get_rate(struct clk *clk)
187 {
188 	return clk->rate;
189 }
190 EXPORT_SYMBOL_GPL(clk_get_rate);
191 
192 int clk_set_rate(struct clk *clk, unsigned long rate)
193 {
194 	return clk_set_rate_ex(clk, rate, 0);
195 }
196 EXPORT_SYMBOL_GPL(clk_set_rate);
197 
198 int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
199 {
200 	int ret = -EOPNOTSUPP;
201 
202 	if (likely(clk->ops && clk->ops->set_rate)) {
203 		unsigned long flags;
204 
205 		spin_lock_irqsave(&clock_lock, flags);
206 		ret = clk->ops->set_rate(clk, rate, algo_id);
207 		spin_unlock_irqrestore(&clock_lock, flags);
208 	}
209 
210 	if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
211 		propagate_rate(clk);
212 
213 	return ret;
214 }
215 EXPORT_SYMBOL_GPL(clk_set_rate_ex);
216 
217 void clk_recalc_rate(struct clk *clk)
218 {
219 	if (likely(clk->ops && clk->ops->recalc)) {
220 		unsigned long flags;
221 
222 		spin_lock_irqsave(&clock_lock, flags);
223 		clk->ops->recalc(clk);
224 		spin_unlock_irqrestore(&clock_lock, flags);
225 	}
226 
227 	if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
228 		propagate_rate(clk);
229 }
230 EXPORT_SYMBOL_GPL(clk_recalc_rate);
231 
232 /*
233  * Returns a clock. Note that we first try to use device id on the bus
234  * and clock name. If this fails, we try to use clock name only.
235  */
236 struct clk *clk_get(struct device *dev, const char *id)
237 {
238 	struct clk *p, *clk = ERR_PTR(-ENOENT);
239 	int idno;
240 
241 	if (dev == NULL || dev->bus != &platform_bus_type)
242 		idno = -1;
243 	else
244 		idno = to_platform_device(dev)->id;
245 
246 	mutex_lock(&clock_list_sem);
247 	list_for_each_entry(p, &clock_list, node) {
248 		if (p->id == idno &&
249 		    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
250 			clk = p;
251 			goto found;
252 		}
253 	}
254 
255 	list_for_each_entry(p, &clock_list, node) {
256 		if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
257 			clk = p;
258 			break;
259 		}
260 	}
261 
262 found:
263 	mutex_unlock(&clock_list_sem);
264 
265 	return clk;
266 }
267 EXPORT_SYMBOL_GPL(clk_get);
268 
269 void clk_put(struct clk *clk)
270 {
271 	if (clk && !IS_ERR(clk))
272 		module_put(clk->owner);
273 }
274 EXPORT_SYMBOL_GPL(clk_put);
275 
276 void __init __attribute__ ((weak))
277 arch_init_clk_ops(struct clk_ops **ops, int type)
278 {
279 }
280 
281 void __init __attribute__ ((weak))
282 arch_clk_init(void)
283 {
284 }
285 
286 static int show_clocks(char *buf, char **start, off_t off,
287 		       int len, int *eof, void *data)
288 {
289 	struct clk *clk;
290 	char *p = buf;
291 
292 	list_for_each_entry_reverse(clk, &clock_list, node) {
293 		unsigned long rate = clk_get_rate(clk);
294 
295 		/*
296 		 * Don't bother listing dummy clocks with no ancestry
297 		 * that only support enable and disable ops.
298 		 */
299 		if (unlikely(!rate && !clk->parent))
300 			continue;
301 
302 		p += sprintf(p, "%-12s\t: %ld.%02ldMHz\n", clk->name,
303 			     rate / 1000000, (rate % 1000000) / 10000);
304 	}
305 
306 	return p - buf;
307 }
308 
309 int __init clk_init(void)
310 {
311 	int i, ret = 0;
312 
313 	BUG_ON(!master_clk.rate);
314 
315 	for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
316 		struct clk *clk = onchip_clocks[i];
317 
318 		arch_init_clk_ops(&clk->ops, i);
319 		ret |= clk_register(clk);
320 	}
321 
322 	arch_clk_init();
323 
324 	/* Kick the child clocks.. */
325 	propagate_rate(&master_clk);
326 	propagate_rate(&bus_clk);
327 
328 	return ret;
329 }
330 
331 static int __init clk_proc_init(void)
332 {
333 	struct proc_dir_entry *p;
334 	p = create_proc_read_entry("clocks", S_IRUSR, NULL,
335 				   show_clocks, NULL);
336 	if (unlikely(!p))
337 		return -EINVAL;
338 
339 	return 0;
340 }
341 subsys_initcall(clk_proc_init);
342