xref: /openbmc/linux/arch/sh/kernel/cpu/clock.c (revision 22246614) 
1 /*
2  * arch/sh/kernel/cpu/clock.c - SuperH clock framework
3  *
4  *  Copyright (C) 2005, 2006, 2007  Paul Mundt
5  *
6  * This clock framework is derived from the OMAP version by:
7  *
8  *	Copyright (C) 2004 - 2005 Nokia Corporation
9  *	Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10  *
11  *  Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
12  *
13  * This file is subject to the terms and conditions of the GNU General Public
14  * License.  See the file "COPYING" in the main directory of this archive
15  * for more details.
16  */
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/mutex.h>
21 #include <linux/list.h>
22 #include <linux/kref.h>
23 #include <linux/seq_file.h>
24 #include <linux/err.h>
25 #include <linux/platform_device.h>
26 #include <linux/proc_fs.h>
27 #include <asm/clock.h>
28 #include <asm/timer.h>
29 
30 static LIST_HEAD(clock_list);
31 static DEFINE_SPINLOCK(clock_lock);
32 static DEFINE_MUTEX(clock_list_sem);
33 
34 /*
35  * Each subtype is expected to define the init routines for these clocks,
36  * as each subtype (or processor family) will have these clocks at the
37  * very least. These are all provided through the CPG, which even some of
38  * the more quirky parts (such as ST40, SH4-202, etc.) still have.
39  *
40  * The processor-specific code is expected to register any additional
41  * clock sources that are of interest.
42  */
43 static struct clk master_clk = {
44 	.name		= "master_clk",
45 	.flags		= CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
46 	.rate		= CONFIG_SH_PCLK_FREQ,
47 };
48 
49 static struct clk module_clk = {
50 	.name		= "module_clk",
51 	.parent		= &master_clk,
52 	.flags		= CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
53 };
54 
55 static struct clk bus_clk = {
56 	.name		= "bus_clk",
57 	.parent		= &master_clk,
58 	.flags		= CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
59 };
60 
61 static struct clk cpu_clk = {
62 	.name		= "cpu_clk",
63 	.parent		= &master_clk,
64 	.flags		= CLK_ALWAYS_ENABLED,
65 };
66 
67 /*
68  * The ordering of these clocks matters, do not change it.
69  */
70 static struct clk *onchip_clocks[] = {
71 	&master_clk,
72 	&module_clk,
73 	&bus_clk,
74 	&cpu_clk,
75 };
76 
77 static void propagate_rate(struct clk *clk)
78 {
79 	struct clk *clkp;
80 
81 	list_for_each_entry(clkp, &clock_list, node) {
82 		if (likely(clkp->parent != clk))
83 			continue;
84 		if (likely(clkp->ops && clkp->ops->recalc))
85 			clkp->ops->recalc(clkp);
86 		if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
87 			propagate_rate(clkp);
88 	}
89 }
90 
91 int __clk_enable(struct clk *clk)
92 {
93 	/*
94 	 * See if this is the first time we're enabling the clock, some
95 	 * clocks that are always enabled still require "special"
96 	 * initialization. This is especially true if the clock mode
97 	 * changes and the clock needs to hunt for the proper set of
98 	 * divisors to use before it can effectively recalc.
99 	 */
100 	if (unlikely(atomic_read(&clk->kref.refcount) == 1))
101 		if (clk->ops && clk->ops->init)
102 			clk->ops->init(clk);
103 
104 	kref_get(&clk->kref);
105 
106 	if (clk->flags & CLK_ALWAYS_ENABLED)
107 		return 0;
108 
109 	if (likely(clk->ops && clk->ops->enable))
110 		clk->ops->enable(clk);
111 
112 	return 0;
113 }
114 EXPORT_SYMBOL_GPL(__clk_enable);
115 
116 int clk_enable(struct clk *clk)
117 {
118 	unsigned long flags;
119 	int ret;
120 
121 	spin_lock_irqsave(&clock_lock, flags);
122 	ret = __clk_enable(clk);
123 	spin_unlock_irqrestore(&clock_lock, flags);
124 
125 	return ret;
126 }
127 EXPORT_SYMBOL_GPL(clk_enable);
128 
129 static void clk_kref_release(struct kref *kref)
130 {
131 	/* Nothing to do */
132 }
133 
134 void __clk_disable(struct clk *clk)
135 {
136 	int count = kref_put(&clk->kref, clk_kref_release);
137 
138 	if (clk->flags & CLK_ALWAYS_ENABLED)
139 		return;
140 
141 	if (!count) {	/* count reaches zero, disable the clock */
142 		if (likely(clk->ops && clk->ops->disable))
143 			clk->ops->disable(clk);
144 	}
145 }
146 EXPORT_SYMBOL_GPL(__clk_disable);
147 
148 void clk_disable(struct clk *clk)
149 {
150 	unsigned long flags;
151 
152 	spin_lock_irqsave(&clock_lock, flags);
153 	__clk_disable(clk);
154 	spin_unlock_irqrestore(&clock_lock, flags);
155 }
156 EXPORT_SYMBOL_GPL(clk_disable);
157 
158 int clk_register(struct clk *clk)
159 {
160 	mutex_lock(&clock_list_sem);
161 
162 	list_add(&clk->node, &clock_list);
163 	kref_init(&clk->kref);
164 
165 	mutex_unlock(&clock_list_sem);
166 
167 	if (clk->flags & CLK_ALWAYS_ENABLED) {
168 		pr_debug( "Clock '%s' is ALWAYS_ENABLED\n", clk->name);
169 		if (clk->ops && clk->ops->init)
170 			clk->ops->init(clk);
171 		if (clk->ops && clk->ops->enable)
172 			clk->ops->enable(clk);
173 		pr_debug( "Enabled.");
174 	}
175 
176 	return 0;
177 }
178 EXPORT_SYMBOL_GPL(clk_register);
179 
180 void clk_unregister(struct clk *clk)
181 {
182 	mutex_lock(&clock_list_sem);
183 	list_del(&clk->node);
184 	mutex_unlock(&clock_list_sem);
185 }
186 EXPORT_SYMBOL_GPL(clk_unregister);
187 
188 unsigned long clk_get_rate(struct clk *clk)
189 {
190 	return clk->rate;
191 }
192 EXPORT_SYMBOL_GPL(clk_get_rate);
193 
194 int clk_set_rate(struct clk *clk, unsigned long rate)
195 {
196 	return clk_set_rate_ex(clk, rate, 0);
197 }
198 EXPORT_SYMBOL_GPL(clk_set_rate);
199 
200 int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
201 {
202 	int ret = -EOPNOTSUPP;
203 
204 	if (likely(clk->ops && clk->ops->set_rate)) {
205 		unsigned long flags;
206 
207 		spin_lock_irqsave(&clock_lock, flags);
208 		ret = clk->ops->set_rate(clk, rate, algo_id);
209 		spin_unlock_irqrestore(&clock_lock, flags);
210 	}
211 
212 	if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
213 		propagate_rate(clk);
214 
215 	return ret;
216 }
217 EXPORT_SYMBOL_GPL(clk_set_rate_ex);
218 
219 void clk_recalc_rate(struct clk *clk)
220 {
221 	if (likely(clk->ops && clk->ops->recalc)) {
222 		unsigned long flags;
223 
224 		spin_lock_irqsave(&clock_lock, flags);
225 		clk->ops->recalc(clk);
226 		spin_unlock_irqrestore(&clock_lock, flags);
227 	}
228 
229 	if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
230 		propagate_rate(clk);
231 }
232 EXPORT_SYMBOL_GPL(clk_recalc_rate);
233 
234 long clk_round_rate(struct clk *clk, unsigned long rate)
235 {
236 	if (likely(clk->ops && clk->ops->round_rate)) {
237 		unsigned long flags, rounded;
238 
239 		spin_lock_irqsave(&clock_lock, flags);
240 		rounded = clk->ops->round_rate(clk, rate);
241 		spin_unlock_irqrestore(&clock_lock, flags);
242 
243 		return rounded;
244 	}
245 
246 	return clk_get_rate(clk);
247 }
248 EXPORT_SYMBOL_GPL(clk_round_rate);
249 
250 /*
251  * Returns a clock. Note that we first try to use device id on the bus
252  * and clock name. If this fails, we try to use clock name only.
253  */
254 struct clk *clk_get(struct device *dev, const char *id)
255 {
256 	struct clk *p, *clk = ERR_PTR(-ENOENT);
257 	int idno;
258 
259 	if (dev == NULL || dev->bus != &platform_bus_type)
260 		idno = -1;
261 	else
262 		idno = to_platform_device(dev)->id;
263 
264 	mutex_lock(&clock_list_sem);
265 	list_for_each_entry(p, &clock_list, node) {
266 		if (p->id == idno &&
267 		    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
268 			clk = p;
269 			goto found;
270 		}
271 	}
272 
273 	list_for_each_entry(p, &clock_list, node) {
274 		if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
275 			clk = p;
276 			break;
277 		}
278 	}
279 
280 found:
281 	mutex_unlock(&clock_list_sem);
282 
283 	return clk;
284 }
285 EXPORT_SYMBOL_GPL(clk_get);
286 
287 void clk_put(struct clk *clk)
288 {
289 	if (clk && !IS_ERR(clk))
290 		module_put(clk->owner);
291 }
292 EXPORT_SYMBOL_GPL(clk_put);
293 
294 void __init __attribute__ ((weak))
295 arch_init_clk_ops(struct clk_ops **ops, int type)
296 {
297 }
298 
299 void __init __attribute__ ((weak))
300 arch_clk_init(void)
301 {
302 }
303 
304 static int show_clocks(char *buf, char **start, off_t off,
305 		       int len, int *eof, void *data)
306 {
307 	struct clk *clk;
308 	char *p = buf;
309 
310 	list_for_each_entry_reverse(clk, &clock_list, node) {
311 		unsigned long rate = clk_get_rate(clk);
312 
313 		/*
314 		 * Don't bother listing dummy clocks with no ancestry
315 		 * that only support enable and disable ops.
316 		 */
317 		if (unlikely(!rate && !clk->parent))
318 			continue;
319 
320 		p += sprintf(p, "%-12s\t: %ld.%02ldMHz\n", clk->name,
321 			     rate / 1000000, (rate % 1000000) / 10000);
322 	}
323 
324 	return p - buf;
325 }
326 
327 int __init clk_init(void)
328 {
329 	int i, ret = 0;
330 
331 	BUG_ON(!master_clk.rate);
332 
333 	for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
334 		struct clk *clk = onchip_clocks[i];
335 
336 		arch_init_clk_ops(&clk->ops, i);
337 		ret |= clk_register(clk);
338 	}
339 
340 	arch_clk_init();
341 
342 	/* Kick the child clocks.. */
343 	propagate_rate(&master_clk);
344 	propagate_rate(&bus_clk);
345 
346 	return ret;
347 }
348 
349 static int __init clk_proc_init(void)
350 {
351 	struct proc_dir_entry *p;
352 	p = create_proc_read_entry("clocks", S_IRUSR, NULL,
353 				   show_clocks, NULL);
354 	if (unlikely(!p))
355 		return -EINVAL;
356 
357 	return 0;
358 }
359 subsys_initcall(clk_proc_init);
360