10a9426dfSDavid Howells #ifndef __ASM_SH_CPU_FEATURES_H 20a9426dfSDavid Howells #define __ASM_SH_CPU_FEATURES_H 30a9426dfSDavid Howells 40a9426dfSDavid Howells /* 50a9426dfSDavid Howells * Processor flags 60a9426dfSDavid Howells * 70a9426dfSDavid Howells * Note: When adding a new flag, keep cpu_flags[] in 80a9426dfSDavid Howells * arch/sh/kernel/setup.c in sync so symbolic name 90a9426dfSDavid Howells * mapping of the processor flags has a chance of being 100a9426dfSDavid Howells * reasonably accurate. 110a9426dfSDavid Howells * 120a9426dfSDavid Howells * These flags are also available through the ELF 130a9426dfSDavid Howells * auxiliary vector as AT_HWCAP. 140a9426dfSDavid Howells */ 150a9426dfSDavid Howells #define CPU_HAS_FPU 0x0001 /* Hardware FPU support */ 160a9426dfSDavid Howells #define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */ 170a9426dfSDavid Howells #define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */ 180a9426dfSDavid Howells #define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */ 190a9426dfSDavid Howells #define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */ 200a9426dfSDavid Howells #define CPU_HAS_PTEA 0x0020 /* PTEA register */ 210a9426dfSDavid Howells #define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */ 220a9426dfSDavid Howells #define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ 230a9426dfSDavid Howells #define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ 240a9426dfSDavid Howells #define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */ 25834da197SRich Felker #define CPU_HAS_CAS_L 0x0400 /* cas.l atomic compare-and-swap */ 260a9426dfSDavid Howells 270a9426dfSDavid Howells #endif /* __ASM_SH_CPU_FEATURES_H */ 28