1 #ifndef __MACH_SDK7786_FPGA_H 2 #define __MACH_SDK7786_FPGA_H 3 4 #include <linux/io.h> 5 #include <linux/types.h> 6 #include <linux/bitops.h> 7 8 #define SRSTR 0x000 9 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */ 10 11 #define INTASR 0x010 12 #define INTAMR 0x020 13 #define MODSWR 0x030 14 #define INTTESTR 0x040 15 #define SYSSR 0x050 16 #define NRGPR 0x060 17 #define NMISR 0x070 18 19 #define NMIMR 0x080 20 #define NMIMR_MAN_NMIM BIT(0) /* Manual NMI mask */ 21 #define NMIMR_AUX_NMIM BIT(1) /* Auxiliary NMI mask */ 22 23 #define INTBSR 0x090 24 #define INTBMR 0x0a0 25 #define USRLEDR 0x0b0 26 #define MAPSWR 0x0c0 27 #define FPGAVR 0x0d0 28 #define FPGADR 0x0e0 29 #define PCBRR 0x0f0 30 #define RSR 0x100 31 #define EXTASR 0x110 32 #define SPCAR 0x120 33 #define INTMSR 0x130 34 #define PCIECR 0x140 35 #define FAER 0x150 36 #define USRGPIR 0x160 37 /* 0x170 reserved */ 38 #define LCLASR 0x180 39 40 #define SBCR 0x190 41 #define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */ 42 #define SCBR_I2CCEN BIT(1) /* CPU I2C master enable */ 43 44 #define PWRCR 0x1a0 45 #define PWRCR_SCISEL0 BIT(0) 46 #define PWRCR_SCISEL1 BIT(1) 47 #define PWRCR_SCIEN BIT(2) /* Serial port enable */ 48 #define PWRCR_PDWNACK BIT(5) /* Power down acknowledge */ 49 #define PWRCR_PDWNREQ BIT(7) /* Power down request */ 50 #define PWRCR_INT2 BIT(11) /* INT2 connection to power manager */ 51 #define PWRCR_BUPINIT BIT(13) /* DDR backup initialize */ 52 #define PWRCR_BKPRST BIT(15) /* Backup power reset */ 53 54 #define SPCBR 0x1b0 55 #define SPICR 0x1c0 56 #define SPIDR 0x1d0 57 #define I2CCR 0x1e0 58 #define I2CDR 0x1f0 59 #define FPGACR 0x200 60 #define IASELR1 0x210 61 #define IASELR2 0x220 62 #define IASELR3 0x230 63 #define IASELR4 0x240 64 #define IASELR5 0x250 65 #define IASELR6 0x260 66 #define IASELR7 0x270 67 #define IASELR8 0x280 68 #define IASELR9 0x290 69 #define IASELR10 0x2a0 70 #define IASELR11 0x2b0 71 #define IASELR12 0x2c0 72 #define IASELR13 0x2d0 73 #define IASELR14 0x2e0 74 #define IASELR15 0x2f0 75 /* 0x300 reserved */ 76 #define IBSELR1 0x310 77 #define IBSELR2 0x320 78 #define IBSELR3 0x330 79 #define IBSELR4 0x340 80 #define IBSELR5 0x350 81 #define IBSELR6 0x360 82 #define IBSELR7 0x370 83 #define IBSELR8 0x380 84 #define IBSELR9 0x390 85 #define IBSELR10 0x3a0 86 #define IBSELR11 0x3b0 87 #define IBSELR12 0x3c0 88 #define IBSELR13 0x3d0 89 #define IBSELR14 0x3e0 90 #define IBSELR15 0x3f0 91 #define USRACR 0x400 92 #define BEEPR 0x410 93 #define USRLCDR 0x420 94 #define SMBCR 0x430 95 #define SMBDR 0x440 96 #define USBCR 0x450 97 #define AMSR 0x460 98 #define ACCR 0x470 99 #define SDIFCR 0x480 100 101 /* arch/sh/boards/mach-sdk7786/fpga.c */ 102 extern void __iomem *sdk7786_fpga_base; 103 extern void sdk7786_fpga_init(void); 104 105 #define SDK7786_FPGA_REGADDR(reg) (sdk7786_fpga_base + (reg)) 106 107 /* 108 * A convenience wrapper from register offset to internal I2C address, 109 * when the FPGA is in I2C slave mode. 110 */ 111 #define SDK7786_FPGA_I2CADDR(reg) ((reg) >> 3) 112 113 static inline u16 fpga_read_reg(unsigned int reg) 114 { 115 return ioread16(sdk7786_fpga_base + reg); 116 } 117 118 static inline void fpga_write_reg(u16 val, unsigned int reg) 119 { 120 iowrite16(val, sdk7786_fpga_base + reg); 121 } 122 123 #endif /* __MACH_SDK7786_FPGA_H */ 124