16a0abce4SKuninori Morimoto /* SPDX-License-Identifier: GPL-2.0 26a0abce4SKuninori Morimoto * 3f15cbe6fSPaul Mundt * include/asm-sh/dreamcast/dma.h 4f15cbe6fSPaul Mundt * 5f15cbe6fSPaul Mundt * Copyright (C) 2003 Paul Mundt 6f15cbe6fSPaul Mundt */ 7f15cbe6fSPaul Mundt #ifndef __ASM_SH_DREAMCAST_DMA_H 8f15cbe6fSPaul Mundt #define __ASM_SH_DREAMCAST_DMA_H 9f15cbe6fSPaul Mundt 10f15cbe6fSPaul Mundt /* Number of DMA channels */ 11f15cbe6fSPaul Mundt #define G2_NR_DMA_CHANNELS 4 12f15cbe6fSPaul Mundt 13f15cbe6fSPaul Mundt /* Channels for cascading */ 14f15cbe6fSPaul Mundt #define PVR2_CASCADE_CHAN 2 15f15cbe6fSPaul Mundt #define G2_CASCADE_CHAN 3 16f15cbe6fSPaul Mundt 17f15cbe6fSPaul Mundt /* PVR2 DMA Registers */ 18f15cbe6fSPaul Mundt #define PVR2_DMA_BASE 0xa05f6800 19f15cbe6fSPaul Mundt #define PVR2_DMA_ADDR (PVR2_DMA_BASE + 0) 20f15cbe6fSPaul Mundt #define PVR2_DMA_COUNT (PVR2_DMA_BASE + 4) 21f15cbe6fSPaul Mundt #define PVR2_DMA_MODE (PVR2_DMA_BASE + 8) 22f15cbe6fSPaul Mundt #define PVR2_DMA_LMMODE0 (PVR2_DMA_BASE + 132) 23f15cbe6fSPaul Mundt #define PVR2_DMA_LMMODE1 (PVR2_DMA_BASE + 136) 24f15cbe6fSPaul Mundt 25f15cbe6fSPaul Mundt /* G2 DMA Register */ 26f15cbe6fSPaul Mundt #define G2_DMA_BASE 0xa05f7800 27f15cbe6fSPaul Mundt 28f15cbe6fSPaul Mundt #endif /* __ASM_SH_DREAMCAST_DMA_H */ 29f15cbe6fSPaul Mundt 30