1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __MACH_URQUELL_H
3 #define __MACH_URQUELL_H
4 
5 /*
6  * ------ 0x00000000 ------------------------------------
7  *  CS0 | (SW1,SW47)    EEPROM, SRAM, NOR FLASH
8  * -----+ 0x04000000 ------------------------------------
9  *  CS1 | (SW47)        SRAM, SRAM-LAN-PCMCIA, NOR FLASH
10  * -----+ 0x08000000 ------------------------------------
11  *  CS2 |               DDR3
12  *  CS3 |
13  * -----+ 0x10000000 ------------------------------------
14  *  CS4 |               PCIe
15  * -----+ 0x14000000 ------------------------------------
16  *  CS5 | (SW47)        LRAM/URAM, SRAM-LAN-PCMCIA
17  * -----+ 0x18000000 ------------------------------------
18  *  CS6 |               ATA, NAND FLASH
19  * -----+ 0x1c000000 ------------------------------------
20  *  CS7 |               SH7786 register
21  * -----+------------------------------------------------
22  */
23 
24 #define NOR_FLASH_ADDR	0x00000000
25 #define NOR_FLASH_SIZE	0x04000000
26 
27 #define CS1_BASE	0x05000000
28 #define CS5_BASE	0x15000000
29 #define FPGA_BASE	CS1_BASE
30 
31 #define BOARDREG(ofs)	(FPGA_BASE + ofs##_OFS)
32 #define UBOARDREG(ofs)	(0xa0000000 + FPGA_BASE + ofs##_OFS)
33 
34 #define SRSTR_OFS	0x0000 /* System reset register */
35 #define BDMR_OFS	0x0010 /* Board operating mode resister */
36 #define IRL0SR_OFS	0x0020 /* IRL0 Status register */
37 #define IRL0MSKR_OFS	0x0030 /* IRL0 Mask register */
38 #define IRL1SR_OFS	0x0040 /* IRL1 Status register */
39 #define IRL1MSKR_OFS	0x0050 /* IRL1 Mask register */
40 #define IRL2SR_OFS	0x0060 /* IRL2 Status register */
41 #define IRL2MSKR_OFS	0x0070 /* IRL2 Mask register */
42 #define IRL3SR_OFS	0x0080 /* IRL3 Status register */
43 #define IRL3MSKR_OFS	0x0090 /* IRL3 Mask register */
44 #define SOFTINTR_OFS	0x0120 /* Softwear Interrupt register */
45 #define SLEDR_OFS	0x0130 /* LED control resister */
46 #define MAPSCIFSWR_OFS	0x0140 /* Map/SCIF Switch register */
47 #define FPVERR_OFS	0x0150 /* FPGA Version register */
48 #define FPDATER_OFS	0x0160 /* FPGA Date register */
49 #define FPYEARR_OFS	0x0170 /* FPGA Year register */
50 #define TCLKCR_OFS	0x0180 /* TCLK Control register */
51 #define DIPSWMR_OFS	0x1000 /* DIPSW monitor register */
52 #define FPODR_OFS	0x1010 /* Output port data register */
53 #define ATACNR_OFS	0x1020 /* ATA-CN Control/status register */
54 #define FPINDR_OFS	0x1030 /* Input port data register */
55 #define MDSWMR_OFS	0x1040 /* MODE SW monitor register */
56 #define DDR3BUPCR_OFS	0x1050 /* DDR3 Backup control register */
57 #define SSICODECCR_OFS	0x1060 /* SSI-CODEC control register */
58 #define PCIESLOTSR_OFS	0x1070 /* PCIexpress Slot status register */
59 #define ETHERPORTSR_OFS	0x1080 /* EtherPhy Port status register */
60 #define LATCHCR_OFS	0x3000 /* Latch control register */
61 #define LATCUAR_OFS	0x3010 /* Latch upper address register */
62 #define LATCLAR_OFS	0x3012 /* Latch lower address register */
63 #define LATCLUDR_OFS	0x3024 /* Latch D31-16 register */
64 #define LATCLLDR_OFS	0x3026 /* Latch D15-0 register */
65 
66 #define CHARLED_OFS	0x2000 /* Character LED */
67 
68 #endif  /* __MACH_URQUELL_H */
69 
70