17639a454SPaul Mundt #ifndef __ASM_SH_RENESAS_SH7785LCR_H 27639a454SPaul Mundt #define __ASM_SH_RENESAS_SH7785LCR_H 37639a454SPaul Mundt 47639a454SPaul Mundt /* 57639a454SPaul Mundt * This board has 2 physical memory maps. 67639a454SPaul Mundt * It can be changed with DIP switch(S2-5). 77639a454SPaul Mundt * 87639a454SPaul Mundt * phys address | S2-5 = OFF | S2-5 = ON 97639a454SPaul Mundt * -----------------------------+---------------+--------------- 107639a454SPaul Mundt * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash 117639a454SPaul Mundt * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD 127639a454SPaul Mundt * 0x06000000 - 0x07ffffff(CS1) | reserved | I2C 137639a454SPaul Mundt * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM 147639a454SPaul Mundt * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM 157639a454SPaul Mundt * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 167639a454SPaul Mundt * 0x14000000 - 0x17ffffff(CS5) | I2C | USB 177639a454SPaul Mundt * 0x18000000 - 0x1bffffff(CS6) | reserved | SD 187639a454SPaul Mundt * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) 197639a454SPaul Mundt * 207639a454SPaul Mundt */ 217639a454SPaul Mundt 227639a454SPaul Mundt #define NOR_FLASH_ADDR 0x00000000 237639a454SPaul Mundt #define NOR_FLASH_SIZE 0x04000000 247639a454SPaul Mundt 257639a454SPaul Mundt #define PLD_BASE_ADDR 0x04000000 267639a454SPaul Mundt #define PLD_PCICR (PLD_BASE_ADDR + 0x00) 277639a454SPaul Mundt #define PLD_LCD_BK_CONTR (PLD_BASE_ADDR + 0x02) 287639a454SPaul Mundt #define PLD_LOCALCR (PLD_BASE_ADDR + 0x04) 297639a454SPaul Mundt #define PLD_POFCR (PLD_BASE_ADDR + 0x06) 307639a454SPaul Mundt #define PLD_LEDCR (PLD_BASE_ADDR + 0x08) 317639a454SPaul Mundt #define PLD_SWSR (PLD_BASE_ADDR + 0x0a) 327639a454SPaul Mundt #define PLD_VERSR (PLD_BASE_ADDR + 0x0c) 337639a454SPaul Mundt #define PLD_MMSR (PLD_BASE_ADDR + 0x0e) 347639a454SPaul Mundt 357639a454SPaul Mundt #define SM107_MEM_ADDR 0x10000000 367639a454SPaul Mundt #define SM107_MEM_SIZE 0x00e00000 377639a454SPaul Mundt #define SM107_REG_ADDR 0x13e00000 387639a454SPaul Mundt #define SM107_REG_SIZE 0x00200000 397639a454SPaul Mundt 407639a454SPaul Mundt #if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS) 417639a454SPaul Mundt #define R8A66597_ADDR 0x14000000 /* USB */ 427639a454SPaul Mundt #define CG200_ADDR 0x18000000 /* SD */ 437639a454SPaul Mundt #define PCA9564_ADDR 0x06000000 /* I2C */ 447639a454SPaul Mundt #else 457639a454SPaul Mundt #define R8A66597_ADDR 0x08000000 467639a454SPaul Mundt #define CG200_ADDR 0x0c000000 477639a454SPaul Mundt #define PCA9564_ADDR 0x14000000 487639a454SPaul Mundt #endif 497639a454SPaul Mundt 507639a454SPaul Mundt #define R8A66597_SIZE 0x00000100 517639a454SPaul Mundt #define CG200_SIZE 0x00010000 527639a454SPaul Mundt #define PCA9564_SIZE 0x00000100 537639a454SPaul Mundt 547639a454SPaul Mundt #endif /* __ASM_SH_RENESAS_SH7785LCR_H */ 557639a454SPaul Mundt 56