1 /* 2 * include/asm-sh/cpu-sh4/mmu_context.h 3 * 4 * Copyright (C) 1999 Niibe Yutaka 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #ifndef __ASM_CPU_SH4_MMU_CONTEXT_H 11 #define __ASM_CPU_SH4_MMU_CONTEXT_H 12 13 #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */ 14 #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ 15 #define MMU_TTB 0xFF000008 /* Translation table base register */ 16 #define MMU_TEA 0xFF00000C /* TLB Exception Address */ 17 #define MMU_PTEA 0xFF000034 /* PTE assistance register */ 18 #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */ 19 20 #define MMUCR 0xFF000010 /* MMU Control Register */ 21 22 #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 23 #define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000 24 #define MMU_PAGE_ASSOC_BIT 0x80 25 26 #define MMUCR_TI (1<<2) 27 28 #if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40) 29 #define MMUCR_SE (1 << 4) 30 #else 31 #define MMUCR_SE (0) 32 #endif 33 34 #ifdef CONFIG_CPU_HAS_PTEAEX 35 #define MMUCR_AEX (1 << 6) 36 #else 37 #define MMUCR_AEX (0) 38 #endif 39 40 #ifdef CONFIG_X2TLB 41 #define MMUCR_ME (1 << 7) 42 #else 43 #define MMUCR_ME (0) 44 #endif 45 46 #ifdef CONFIG_SH_STORE_QUEUES 47 #define MMUCR_SQMD (1 << 9) 48 #else 49 #define MMUCR_SQMD (0) 50 #endif 51 52 #define MMU_NTLB_ENTRIES 64 53 #define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE|MMUCR_AEX) 54 55 #define TRA 0xff000020 56 #define EXPEVT 0xff000024 57 #define INTEVT 0xff000028 58 59 #endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */ 60 61