1 /* 2 * include/asm-sh/cpu-sh4/freq.h 3 * 4 * Copyright (C) 2002, 2003 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #ifndef __ASM_CPU_SH4_FREQ_H 11 #define __ASM_CPU_SH4_FREQ_H 12 13 #if defined(CONFIG_CPU_SUBTYPE_SH7722) || \ 14 defined(CONFIG_CPU_SUBTYPE_SH7723) || \ 15 defined(CONFIG_CPU_SUBTYPE_SH7343) || \ 16 defined(CONFIG_CPU_SUBTYPE_SH7366) 17 #define FRQCR 0xa4150000 18 #define VCLKCR 0xa4150004 19 #define SCLKACR 0xa4150008 20 #define SCLKBCR 0xa415000c 21 #define IrDACLKCR 0xa4150010 22 #define MSTPCR0 0xa4150030 23 #define MSTPCR1 0xa4150034 24 #define MSTPCR2 0xa4150038 25 #elif defined(CONFIG_CPU_SUBTYPE_SH7757) 26 #define FRQCR 0xffc80000 27 #define OSCCR 0xffc80018 28 #define PLLCR 0xffc80024 29 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 30 defined(CONFIG_CPU_SUBTYPE_SH7780) 31 #define FRQCR 0xffc80000 32 #elif defined(CONFIG_CPU_SUBTYPE_SH7724) 33 #define FRQCRA 0xa4150000 34 #define FRQCRB 0xa4150004 35 #define VCLKCR 0xa4150048 36 37 #define FCLKACR 0xa4150008 38 #define FCLKBCR 0xa415000c 39 #define FRQCR FRQCRA 40 #define SCLKACR FCLKACR 41 #define SCLKBCR FCLKBCR 42 #define FCLKACR 0xa4150008 43 #define FCLKBCR 0xa415000c 44 #define IrDACLKCR 0xa4150018 45 46 #define MSTPCR0 0xa4150030 47 #define MSTPCR1 0xa4150034 48 #define MSTPCR2 0xa4150038 49 50 #elif defined(CONFIG_CPU_SUBTYPE_SH7734) 51 #define FRQCR0 0xffc80000 52 #define FRQCR2 0xffc80008 53 #define FRQMR1 0xffc80014 54 #define FRQMR2 0xffc80018 55 #elif defined(CONFIG_CPU_SUBTYPE_SH7785) 56 #define FRQCR0 0xffc80000 57 #define FRQCR1 0xffc80004 58 #define FRQMR1 0xffc80014 59 #elif defined(CONFIG_CPU_SUBTYPE_SH7786) 60 #define FRQCR0 0xffc40000 61 #define FRQCR1 0xffc40004 62 #define FRQMR1 0xffc40014 63 #elif defined(CONFIG_CPU_SUBTYPE_SHX3) 64 #define FRQCR0 0xffc00000 65 #define FRQCR1 0xffc00004 66 #define FRQMR1 0xffc00014 67 #else 68 #define FRQCR 0xffc00000 69 #define FRQCR_PSTBY 0x0200 70 #define FRQCR_PLLEN 0x0400 71 #define FRQCR_CKOEN 0x0800 72 #endif 73 #define MIN_DIVISOR_NR 0 74 #define MAX_DIVISOR_NR 3 75 76 #endif /* __ASM_CPU_SH4_FREQ_H */ 77 78