1 #ifndef __ASM_CPU_SH4_DMA_H 2 #define __ASM_CPU_SH4_DMA_H 3 4 /* SH7751/7760/7780 DMA IRQ sources */ 5 6 #ifdef CONFIG_CPU_SH4A 7 8 #define DMAOR_INIT (DMAOR_DME) 9 #define CHCR_TS_MASK 0x18 10 #define CHCR_TS_SHIFT 3 11 12 #include <cpu/dma-sh4a.h> 13 #else /* CONFIG_CPU_SH4A */ 14 /* 15 * SH7750/SH7751/SH7760 16 */ 17 #define DMTE0_IRQ 34 18 #define DMTE4_IRQ 44 19 #define DMTE6_IRQ 46 20 #define DMAE0_IRQ 38 21 22 #define DMAOR_INIT (0x8000|DMAOR_DME) 23 #define SH_DMAC_BASE0 0xffa00000 24 #define SH_DMAC_BASE1 0xffa00070 25 /* Definitions for the SuperH DMAC */ 26 #define TM_BURST 0x00000080 27 #define TS_8 0x00000010 28 #define TS_16 0x00000020 29 #define TS_32 0x00000030 30 #define TS_64 0x00000000 31 32 #define CHCR_TS_MASK 0x70 33 #define CHCR_TS_SHIFT 4 34 35 #define DMAOR_COD 0x00000008 36 37 /* 38 * The SuperH DMAC supports a number of transmit sizes, we list them here, 39 * with their respective values as they appear in the CHCR registers. 40 * 41 * Defaults to a 64-bit transfer size. 42 */ 43 enum { 44 XMIT_SZ_64BIT, 45 XMIT_SZ_8BIT, 46 XMIT_SZ_16BIT, 47 XMIT_SZ_32BIT, 48 XMIT_SZ_256BIT, 49 }; 50 51 /* 52 * The DMA count is defined as the number of bytes to transfer. 53 */ 54 static unsigned int ts_shift[] __maybe_unused = { 55 [XMIT_SZ_64BIT] = 3, 56 [XMIT_SZ_8BIT] = 0, 57 [XMIT_SZ_16BIT] = 1, 58 [XMIT_SZ_32BIT] = 2, 59 [XMIT_SZ_256BIT] = 5, 60 }; 61 #endif 62 63 #endif /* __ASM_CPU_SH4_DMA_H */ 64