18b1935e6SGuennadi Liakhovetski /* 28b1935e6SGuennadi Liakhovetski * SH4 CPU-specific DMA definitions, used by both DMA drivers 38b1935e6SGuennadi Liakhovetski * 48b1935e6SGuennadi Liakhovetski * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 58b1935e6SGuennadi Liakhovetski * 68b1935e6SGuennadi Liakhovetski * This program is free software; you can redistribute it and/or modify 78b1935e6SGuennadi Liakhovetski * it under the terms of the GNU General Public License version 2 as 88b1935e6SGuennadi Liakhovetski * published by the Free Software Foundation. 98b1935e6SGuennadi Liakhovetski */ 108b1935e6SGuennadi Liakhovetski #ifndef CPU_DMA_REGISTER_H 118b1935e6SGuennadi Liakhovetski #define CPU_DMA_REGISTER_H 128b1935e6SGuennadi Liakhovetski 138b1935e6SGuennadi Liakhovetski /* SH7751/7760/7780 DMA IRQ sources */ 148b1935e6SGuennadi Liakhovetski 158b1935e6SGuennadi Liakhovetski #ifdef CONFIG_CPU_SH4A 168b1935e6SGuennadi Liakhovetski 178b1935e6SGuennadi Liakhovetski #define DMAOR_INIT DMAOR_DME 188b1935e6SGuennadi Liakhovetski 199cdb81c7SNobuhiro Iwamatsu #if defined(CONFIG_CPU_SUBTYPE_SH7343) 208b1935e6SGuennadi Liakhovetski #define CHCR_TS_LOW_MASK 0x00000018 218b1935e6SGuennadi Liakhovetski #define CHCR_TS_LOW_SHIFT 3 228b1935e6SGuennadi Liakhovetski #define CHCR_TS_HIGH_MASK 0 238b1935e6SGuennadi Liakhovetski #define CHCR_TS_HIGH_SHIFT 0 24c8e3149bSGuennadi Liakhovetski #elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \ 259cdb81c7SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7723) || \ 26050d4cc7SPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7724) || \ 279cdb81c7SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7730) || \ 28050d4cc7SPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7786) 298b1935e6SGuennadi Liakhovetski #define CHCR_TS_LOW_MASK 0x00000018 308b1935e6SGuennadi Liakhovetski #define CHCR_TS_LOW_SHIFT 3 318b1935e6SGuennadi Liakhovetski #define CHCR_TS_HIGH_MASK 0x00300000 328b1935e6SGuennadi Liakhovetski #define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ 33ffe0e190SNobuhiro Iwamatsu #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \ 34ffe0e190SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 35ffe0e190SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7764) || \ 36ffe0e190SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 37ffe0e190SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7785) 388ac53ed5SYoshihiro Shimoda #define CHCR_TS_LOW_MASK 0x00000018 398ac53ed5SYoshihiro Shimoda #define CHCR_TS_LOW_SHIFT 3 408ac53ed5SYoshihiro Shimoda #define CHCR_TS_HIGH_MASK 0x00100000 418ac53ed5SYoshihiro Shimoda #define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */ 428b1935e6SGuennadi Liakhovetski #endif 438b1935e6SGuennadi Liakhovetski 448b1935e6SGuennadi Liakhovetski /* Transmit sizes and respective CHCR register values */ 458b1935e6SGuennadi Liakhovetski enum { 468b1935e6SGuennadi Liakhovetski XMIT_SZ_8BIT = 0, 478b1935e6SGuennadi Liakhovetski XMIT_SZ_16BIT = 1, 488b1935e6SGuennadi Liakhovetski XMIT_SZ_32BIT = 2, 498b1935e6SGuennadi Liakhovetski XMIT_SZ_64BIT = 7, 508b1935e6SGuennadi Liakhovetski XMIT_SZ_128BIT = 3, 518b1935e6SGuennadi Liakhovetski XMIT_SZ_256BIT = 4, 528b1935e6SGuennadi Liakhovetski XMIT_SZ_128BIT_BLK = 0xb, 538b1935e6SGuennadi Liakhovetski XMIT_SZ_256BIT_BLK = 0xc, 548b1935e6SGuennadi Liakhovetski }; 558b1935e6SGuennadi Liakhovetski 568b1935e6SGuennadi Liakhovetski /* log2(size / 8) - used to calculate number of transfers */ 578b1935e6SGuennadi Liakhovetski #define TS_SHIFT { \ 588b1935e6SGuennadi Liakhovetski [XMIT_SZ_8BIT] = 0, \ 598b1935e6SGuennadi Liakhovetski [XMIT_SZ_16BIT] = 1, \ 608b1935e6SGuennadi Liakhovetski [XMIT_SZ_32BIT] = 2, \ 618b1935e6SGuennadi Liakhovetski [XMIT_SZ_64BIT] = 3, \ 628b1935e6SGuennadi Liakhovetski [XMIT_SZ_128BIT] = 4, \ 638b1935e6SGuennadi Liakhovetski [XMIT_SZ_256BIT] = 5, \ 648b1935e6SGuennadi Liakhovetski [XMIT_SZ_128BIT_BLK] = 4, \ 658b1935e6SGuennadi Liakhovetski [XMIT_SZ_256BIT_BLK] = 5, \ 668b1935e6SGuennadi Liakhovetski } 678b1935e6SGuennadi Liakhovetski 688b1935e6SGuennadi Liakhovetski #define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \ 69c2fe3092SGuennadi Liakhovetski (((i) & 0xc) << CHCR_TS_HIGH_SHIFT)) 708b1935e6SGuennadi Liakhovetski 718b1935e6SGuennadi Liakhovetski #else /* CONFIG_CPU_SH4A */ 728b1935e6SGuennadi Liakhovetski 738b1935e6SGuennadi Liakhovetski #define DMAOR_INIT (0x8000 | DMAOR_DME) 748b1935e6SGuennadi Liakhovetski 758b1935e6SGuennadi Liakhovetski #define CHCR_TS_LOW_MASK 0x70 768b1935e6SGuennadi Liakhovetski #define CHCR_TS_LOW_SHIFT 4 778b1935e6SGuennadi Liakhovetski #define CHCR_TS_HIGH_MASK 0 788b1935e6SGuennadi Liakhovetski #define CHCR_TS_HIGH_SHIFT 0 798b1935e6SGuennadi Liakhovetski 808b1935e6SGuennadi Liakhovetski /* Transmit sizes and respective CHCR register values */ 818b1935e6SGuennadi Liakhovetski enum { 828b1935e6SGuennadi Liakhovetski XMIT_SZ_8BIT = 1, 838b1935e6SGuennadi Liakhovetski XMIT_SZ_16BIT = 2, 848b1935e6SGuennadi Liakhovetski XMIT_SZ_32BIT = 3, 858b1935e6SGuennadi Liakhovetski XMIT_SZ_64BIT = 0, 868b1935e6SGuennadi Liakhovetski XMIT_SZ_256BIT = 4, 878b1935e6SGuennadi Liakhovetski }; 888b1935e6SGuennadi Liakhovetski 898b1935e6SGuennadi Liakhovetski /* log2(size / 8) - used to calculate number of transfers */ 908b1935e6SGuennadi Liakhovetski #define TS_SHIFT { \ 918b1935e6SGuennadi Liakhovetski [XMIT_SZ_8BIT] = 0, \ 928b1935e6SGuennadi Liakhovetski [XMIT_SZ_16BIT] = 1, \ 938b1935e6SGuennadi Liakhovetski [XMIT_SZ_32BIT] = 2, \ 948b1935e6SGuennadi Liakhovetski [XMIT_SZ_64BIT] = 3, \ 958b1935e6SGuennadi Liakhovetski [XMIT_SZ_256BIT] = 5, \ 968b1935e6SGuennadi Liakhovetski } 978b1935e6SGuennadi Liakhovetski 988b1935e6SGuennadi Liakhovetski #define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT) 998b1935e6SGuennadi Liakhovetski 1008b1935e6SGuennadi Liakhovetski #endif /* CONFIG_CPU_SH4A */ 1018b1935e6SGuennadi Liakhovetski 1028b1935e6SGuennadi Liakhovetski #endif 103