1 /* 2 * include/asm-sh/cpu-sh4/cache.h 3 * 4 * Copyright (C) 1999 Niibe Yutaka 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #ifndef __ASM_CPU_SH4_CACHE_H 11 #define __ASM_CPU_SH4_CACHE_H 12 13 #define L1_CACHE_SHIFT 5 14 15 #define SH_CACHE_VALID 1 16 #define SH_CACHE_UPDATED 2 17 #define SH_CACHE_COMBINED 4 18 #define SH_CACHE_ASSOC 8 19 20 #define CCR 0xff00001c /* Address of Cache Control Register */ 21 #define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */ 22 #define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/ 23 #define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */ 24 #define CCR_CACHE_OCI 0x0008 /* OC Invalidate */ 25 #define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */ 26 #define CCR_CACHE_OIX 0x0080 /* OC Index Enable */ 27 #define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */ 28 #define CCR_CACHE_ICI 0x0800 /* IC Invalidate */ 29 #define CCR_CACHE_IIX 0x8000 /* IC Index Enable */ 30 #ifndef CONFIG_CPU_SH4A 31 #define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */ 32 #endif 33 34 /* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */ 35 #define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE) 36 #define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI) 37 38 #define CACHE_IC_ADDRESS_ARRAY 0xf0000000 39 #define CACHE_OC_ADDRESS_ARRAY 0xf4000000 40 41 #define RAMCR 0xFF000074 42 43 #endif /* __ASM_CPU_SH4_CACHE_H */ 44 45