1f15cbe6fSPaul Mundt #ifndef __ASM_CPU_SH3_DMA_H 2f15cbe6fSPaul Mundt #define __ASM_CPU_SH3_DMA_H 3f15cbe6fSPaul Mundt 4f15cbe6fSPaul Mundt 5f15cbe6fSPaul Mundt #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 6f15cbe6fSPaul Mundt defined(CONFIG_CPU_SUBTYPE_SH7721) 7f15cbe6fSPaul Mundt #define SH_DMAC_BASE 0xa4010020 8f15cbe6fSPaul Mundt #else 9f15cbe6fSPaul Mundt #define SH_DMAC_BASE 0xa4000020 10f15cbe6fSPaul Mundt #endif 11f15cbe6fSPaul Mundt 12f15cbe6fSPaul Mundt #if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709) 13f15cbe6fSPaul Mundt #define DMTE0_IRQ 48 14f15cbe6fSPaul Mundt #define DMTE1_IRQ 49 15f15cbe6fSPaul Mundt #define DMTE2_IRQ 50 16f15cbe6fSPaul Mundt #define DMTE3_IRQ 51 17f15cbe6fSPaul Mundt #define DMTE4_IRQ 76 18f15cbe6fSPaul Mundt #define DMTE5_IRQ 77 19f15cbe6fSPaul Mundt #endif 20f15cbe6fSPaul Mundt 21f15cbe6fSPaul Mundt /* Definitions for the SuperH DMAC */ 22f15cbe6fSPaul Mundt #define TM_BURST 0x00000020 23f15cbe6fSPaul Mundt #define TS_8 0x00000000 24f15cbe6fSPaul Mundt #define TS_16 0x00000008 25f15cbe6fSPaul Mundt #define TS_32 0x00000010 26f15cbe6fSPaul Mundt #define TS_128 0x00000018 27f15cbe6fSPaul Mundt 28f15cbe6fSPaul Mundt #define CHCR_TS_MASK 0x18 29f15cbe6fSPaul Mundt #define CHCR_TS_SHIFT 3 30f15cbe6fSPaul Mundt 31f15cbe6fSPaul Mundt #define DMAOR_INIT DMAOR_DME 32f15cbe6fSPaul Mundt 33f15cbe6fSPaul Mundt /* 34f15cbe6fSPaul Mundt * The SuperH DMAC supports a number of transmit sizes, we list them here, 35f15cbe6fSPaul Mundt * with their respective values as they appear in the CHCR registers. 36f15cbe6fSPaul Mundt */ 37f15cbe6fSPaul Mundt enum { 38f15cbe6fSPaul Mundt XMIT_SZ_8BIT, 39f15cbe6fSPaul Mundt XMIT_SZ_16BIT, 40f15cbe6fSPaul Mundt XMIT_SZ_32BIT, 41f15cbe6fSPaul Mundt XMIT_SZ_128BIT, 42f15cbe6fSPaul Mundt }; 43f15cbe6fSPaul Mundt 44f15cbe6fSPaul Mundt static unsigned int ts_shift[] __maybe_unused = { 45f15cbe6fSPaul Mundt [XMIT_SZ_8BIT] = 0, 46f15cbe6fSPaul Mundt [XMIT_SZ_16BIT] = 1, 47f15cbe6fSPaul Mundt [XMIT_SZ_32BIT] = 2, 48f15cbe6fSPaul Mundt [XMIT_SZ_128BIT] = 4, 49f15cbe6fSPaul Mundt }; 50f15cbe6fSPaul Mundt 51f15cbe6fSPaul Mundt #endif /* __ASM_CPU_SH3_DMA_H */ 52