1f15cbe6fSPaul Mundt #ifndef __ASM_CPU_SH3_DMA_H 2f15cbe6fSPaul Mundt #define __ASM_CPU_SH3_DMA_H 3f15cbe6fSPaul Mundt 4f15cbe6fSPaul Mundt #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 571b973a4SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 671b973a4SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 771b973a4SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7712) 871b973a4SNobuhiro Iwamatsu #define SH_DMAC_BASE0 0xa4010020 971b973a4SNobuhiro Iwamatsu #else /* SH7705/06/07/09 */ 1071b973a4SNobuhiro Iwamatsu #define SH_DMAC_BASE0 0xa4000020 11f15cbe6fSPaul Mundt #endif 12f15cbe6fSPaul Mundt 13f15cbe6fSPaul Mundt #define DMTE0_IRQ 48 14f15cbe6fSPaul Mundt #define DMTE4_IRQ 76 15f15cbe6fSPaul Mundt 16f15cbe6fSPaul Mundt /* Definitions for the SuperH DMAC */ 17f15cbe6fSPaul Mundt #define TM_BURST 0x00000020 18f15cbe6fSPaul Mundt #define TS_8 0x00000000 19f15cbe6fSPaul Mundt #define TS_16 0x00000008 20f15cbe6fSPaul Mundt #define TS_32 0x00000010 21f15cbe6fSPaul Mundt #define TS_128 0x00000018 22f15cbe6fSPaul Mundt 23f15cbe6fSPaul Mundt #define CHCR_TS_MASK 0x18 24f15cbe6fSPaul Mundt #define CHCR_TS_SHIFT 3 25f15cbe6fSPaul Mundt 26f15cbe6fSPaul Mundt #define DMAOR_INIT DMAOR_DME 27f15cbe6fSPaul Mundt 28f15cbe6fSPaul Mundt /* 29f15cbe6fSPaul Mundt * The SuperH DMAC supports a number of transmit sizes, we list them here, 30f15cbe6fSPaul Mundt * with their respective values as they appear in the CHCR registers. 31f15cbe6fSPaul Mundt */ 32f15cbe6fSPaul Mundt enum { 33f15cbe6fSPaul Mundt XMIT_SZ_8BIT, 34f15cbe6fSPaul Mundt XMIT_SZ_16BIT, 35f15cbe6fSPaul Mundt XMIT_SZ_32BIT, 36f15cbe6fSPaul Mundt XMIT_SZ_128BIT, 37f15cbe6fSPaul Mundt }; 38f15cbe6fSPaul Mundt 39f15cbe6fSPaul Mundt static unsigned int ts_shift[] __maybe_unused = { 40f15cbe6fSPaul Mundt [XMIT_SZ_8BIT] = 0, 41f15cbe6fSPaul Mundt [XMIT_SZ_16BIT] = 1, 42f15cbe6fSPaul Mundt [XMIT_SZ_32BIT] = 2, 43f15cbe6fSPaul Mundt [XMIT_SZ_128BIT] = 4, 44f15cbe6fSPaul Mundt }; 45f15cbe6fSPaul Mundt 46f15cbe6fSPaul Mundt #endif /* __ASM_CPU_SH3_DMA_H */ 47