1 /* 2 * include/asm-sh/watchdog.h 3 * 4 * Copyright (C) 2002, 2003 Paul Mundt 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 #ifndef __ASM_SH_WATCHDOG_H 12 #define __ASM_SH_WATCHDOG_H 13 #ifdef __KERNEL__ 14 15 #include <linux/types.h> 16 #include <linux/io.h> 17 18 #define WTCNT_HIGH 0x5a 19 #define WTCSR_HIGH 0xa5 20 21 #define WTCSR_CKS2 0x04 22 #define WTCSR_CKS1 0x02 23 #define WTCSR_CKS0 0x01 24 25 #include <cpu/watchdog.h> 26 27 /* 28 * See cpu-sh2/watchdog.h for explanation of this stupidity.. 29 */ 30 #ifndef WTCNT_R 31 # define WTCNT_R WTCNT 32 #endif 33 34 #ifndef WTCSR_R 35 # define WTCSR_R WTCSR 36 #endif 37 38 /* 39 * CKS0-2 supports a number of clock division ratios. At the time the watchdog 40 * is enabled, it defaults to a 41 usec overflow period .. we overload this to 41 * something a little more reasonable, and really can't deal with anything 42 * lower than WTCSR_CKS_1024, else we drop back into the usec range. 43 * 44 * Clock Division Ratio Overflow Period 45 * -------------------------------------------- 46 * 1/32 (initial value) 41 usecs 47 * 1/64 82 usecs 48 * 1/128 164 usecs 49 * 1/256 328 usecs 50 * 1/512 656 usecs 51 * 1/1024 1.31 msecs 52 * 1/2048 2.62 msecs 53 * 1/4096 5.25 msecs 54 */ 55 #define WTCSR_CKS_32 0x00 56 #define WTCSR_CKS_64 0x01 57 #define WTCSR_CKS_128 0x02 58 #define WTCSR_CKS_256 0x03 59 #define WTCSR_CKS_512 0x04 60 #define WTCSR_CKS_1024 0x05 61 #define WTCSR_CKS_2048 0x06 62 #define WTCSR_CKS_4096 0x07 63 64 /** 65 * sh_wdt_read_cnt - Read from Counter 66 * Reads back the WTCNT value. 67 */ 68 static inline __u8 sh_wdt_read_cnt(void) 69 { 70 return ctrl_inb(WTCNT_R); 71 } 72 73 /** 74 * sh_wdt_write_cnt - Write to Counter 75 * @val: Value to write 76 * 77 * Writes the given value @val to the lower byte of the timer counter. 78 * The upper byte is set manually on each write. 79 */ 80 static inline void sh_wdt_write_cnt(__u8 val) 81 { 82 ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, WTCNT); 83 } 84 85 /** 86 * sh_wdt_read_csr - Read from Control/Status Register 87 * 88 * Reads back the WTCSR value. 89 */ 90 static inline __u8 sh_wdt_read_csr(void) 91 { 92 return ctrl_inb(WTCSR_R); 93 } 94 95 /** 96 * sh_wdt_write_csr - Write to Control/Status Register 97 * @val: Value to write 98 * 99 * Writes the given value @val to the lower byte of the control/status 100 * register. The upper byte is set manually on each write. 101 */ 102 static inline void sh_wdt_write_csr(__u8 val) 103 { 104 ctrl_outw((WTCSR_HIGH << 8) | (__u16)val, WTCSR); 105 } 106 107 #endif /* __KERNEL__ */ 108 #endif /* __ASM_SH_WATCHDOG_H */ 109