1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_SH_PROCESSOR_H 3 #define __ASM_SH_PROCESSOR_H 4 5 #include <asm/cpu-features.h> 6 #include <asm/cache.h> 7 8 #ifndef __ASSEMBLY__ 9 /* 10 * CPU type and hardware bug flags. Kept separately for each CPU. 11 * 12 * Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry 13 * in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c 14 * for parsing the subtype in get_cpu_subtype(). 15 */ 16 enum cpu_type { 17 /* SH-2 types */ 18 CPU_SH7619, CPU_J2, 19 20 /* SH-2A types */ 21 CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269, 22 CPU_MXG, 23 24 /* SH-3 types */ 25 CPU_SH7705, CPU_SH7706, CPU_SH7707, 26 CPU_SH7708, CPU_SH7708S, CPU_SH7708R, 27 CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, 28 CPU_SH7720, CPU_SH7721, CPU_SH7729, 29 30 /* SH-4 types */ 31 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, 32 CPU_SH7760, CPU_SH4_202, CPU_SH4_501, 33 34 /* SH-4A types */ 35 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, 36 CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3, 37 38 /* SH4AL-DSP types */ 39 CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372, 40 41 /* Unknown subtype */ 42 CPU_SH_NONE 43 }; 44 45 enum cpu_family { 46 CPU_FAMILY_SH2, 47 CPU_FAMILY_SH2A, 48 CPU_FAMILY_SH3, 49 CPU_FAMILY_SH4, 50 CPU_FAMILY_SH4A, 51 CPU_FAMILY_SH4AL_DSP, 52 CPU_FAMILY_UNKNOWN, 53 }; 54 55 /* 56 * TLB information structure 57 * 58 * Defined for both I and D tlb, per-processor. 59 */ 60 struct tlb_info { 61 unsigned long long next; 62 unsigned long long first; 63 unsigned long long last; 64 65 unsigned int entries; 66 unsigned int step; 67 68 unsigned long flags; 69 }; 70 71 struct sh_cpuinfo { 72 unsigned int type, family; 73 int cut_major, cut_minor; 74 unsigned long loops_per_jiffy; 75 unsigned long asid_cache; 76 77 struct cache_info icache; /* Primary I-cache */ 78 struct cache_info dcache; /* Primary D-cache */ 79 struct cache_info scache; /* Secondary cache */ 80 81 /* TLB info */ 82 struct tlb_info itlb; 83 struct tlb_info dtlb; 84 85 unsigned int phys_bits; 86 unsigned long flags; 87 } __attribute__ ((aligned(L1_CACHE_BYTES))); 88 89 extern struct sh_cpuinfo cpu_data[]; 90 #define boot_cpu_data cpu_data[0] 91 #define current_cpu_data cpu_data[smp_processor_id()] 92 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()] 93 94 #define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory") 95 #define cpu_relax() barrier() 96 97 void default_idle(void); 98 void stop_this_cpu(void *); 99 100 /* Forward decl */ 101 struct seq_operations; 102 struct task_struct; 103 104 extern struct pt_regs fake_swapper_regs; 105 106 extern void cpu_init(void); 107 extern void cpu_probe(void); 108 109 /* arch/sh/kernel/process.c */ 110 extern unsigned int xstate_size; 111 extern void free_thread_xstate(struct task_struct *); 112 extern struct kmem_cache *task_xstate_cachep; 113 114 /* arch/sh/mm/alignment.c */ 115 extern int get_unalign_ctl(struct task_struct *, unsigned long addr); 116 extern int set_unalign_ctl(struct task_struct *, unsigned int val); 117 118 #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) 119 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) 120 121 /* arch/sh/mm/init.c */ 122 extern unsigned int mem_init_done; 123 124 /* arch/sh/kernel/setup.c */ 125 const char *get_cpu_subtype(struct sh_cpuinfo *c); 126 extern const struct seq_operations cpuinfo_op; 127 128 /* thread_struct flags */ 129 #define SH_THREAD_UAC_NOPRINT (1 << 0) 130 #define SH_THREAD_UAC_SIGBUS (1 << 1) 131 #define SH_THREAD_UAC_MASK (SH_THREAD_UAC_NOPRINT | SH_THREAD_UAC_SIGBUS) 132 133 /* processor boot mode configuration */ 134 #define MODE_PIN0 (1 << 0) 135 #define MODE_PIN1 (1 << 1) 136 #define MODE_PIN2 (1 << 2) 137 #define MODE_PIN3 (1 << 3) 138 #define MODE_PIN4 (1 << 4) 139 #define MODE_PIN5 (1 << 5) 140 #define MODE_PIN6 (1 << 6) 141 #define MODE_PIN7 (1 << 7) 142 #define MODE_PIN8 (1 << 8) 143 #define MODE_PIN9 (1 << 9) 144 #define MODE_PIN10 (1 << 10) 145 #define MODE_PIN11 (1 << 11) 146 #define MODE_PIN12 (1 << 12) 147 #define MODE_PIN13 (1 << 13) 148 #define MODE_PIN14 (1 << 14) 149 #define MODE_PIN15 (1 << 15) 150 151 int generic_mode_pins(void); 152 int test_mode_pin(int pin); 153 154 #ifdef CONFIG_VSYSCALL 155 int vsyscall_init(void); 156 #else 157 #define vsyscall_init() do { } while (0) 158 #endif 159 160 /* 161 * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks. 162 */ 163 #ifdef CONFIG_CPU_SH2A 164 extern unsigned int instruction_size(unsigned int insn); 165 #else 166 #define instruction_size(insn) (2) 167 #endif 168 169 void select_idle_routine(void); 170 171 #endif /* __ASSEMBLY__ */ 172 173 #include <asm/processor_32.h> 174 175 #endif /* __ASM_SH_PROCESSOR_H */ 176