1 /* 2 * This file contains the functions and defines necessary to modify and 3 * use the SuperH page table tree. 4 * 5 * Copyright (C) 1999 Niibe Yutaka 6 * Copyright (C) 2002 - 2007 Paul Mundt 7 * 8 * This file is subject to the terms and conditions of the GNU General 9 * Public License. See the file "COPYING" in the main directory of this 10 * archive for more details. 11 */ 12 #ifndef __ASM_SH_PGTABLE_H 13 #define __ASM_SH_PGTABLE_H 14 15 #include <asm-generic/pgtable-nopmd.h> 16 #include <asm/page.h> 17 18 #ifndef __ASSEMBLY__ 19 #include <asm/addrspace.h> 20 #include <asm/fixmap.h> 21 22 /* 23 * ZERO_PAGE is a global shared page that is always zero: used 24 * for zero-mapped memory areas etc.. 25 */ 26 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; 27 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 28 29 #endif /* !__ASSEMBLY__ */ 30 31 /* 32 * Effective and physical address definitions, to aid with sign 33 * extension. 34 */ 35 #define NEFF 32 36 #define NEFF_SIGN (1LL << (NEFF - 1)) 37 #define NEFF_MASK (-1LL << NEFF) 38 39 static inline unsigned long long neff_sign_extend(unsigned long val) 40 { 41 unsigned long long extended = val; 42 return (extended & NEFF_SIGN) ? (extended | NEFF_MASK) : extended; 43 } 44 45 #ifdef CONFIG_29BIT 46 #define NPHYS 29 47 #else 48 #define NPHYS 32 49 #endif 50 51 #define NPHYS_SIGN (1LL << (NPHYS - 1)) 52 #define NPHYS_MASK (-1LL << NPHYS) 53 54 /* 55 * traditional two-level paging structure 56 */ 57 /* PTE bits */ 58 #if defined(CONFIG_X2TLB) || defined(CONFIG_SUPERH64) 59 # define PTE_MAGNITUDE 3 /* 64-bit PTEs on extended mode SH-X2 TLB */ 60 #else 61 # define PTE_MAGNITUDE 2 /* 32-bit PTEs */ 62 #endif 63 #define PTE_SHIFT PAGE_SHIFT 64 #define PTE_BITS (PTE_SHIFT - PTE_MAGNITUDE) 65 66 /* PGD bits */ 67 #define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS) 68 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 69 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 70 71 /* Entries per level */ 72 #define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE)) 73 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) 74 75 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) 76 #define FIRST_USER_ADDRESS 0 77 78 #ifdef CONFIG_32BIT 79 #define PHYS_ADDR_MASK 0xffffffff 80 #else 81 #define PHYS_ADDR_MASK 0x1fffffff 82 #endif 83 84 #define PTE_PHYS_MASK (PHYS_ADDR_MASK & PAGE_MASK) 85 #define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT) 86 87 #ifdef CONFIG_SUPERH32 88 #define VMALLOC_START (P3SEG) 89 #else 90 #define VMALLOC_START (0xf0000000) 91 #endif 92 #define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) 93 94 #if defined(CONFIG_SUPERH32) 95 #include <asm/pgtable_32.h> 96 #else 97 #include <asm/pgtable_64.h> 98 #endif 99 100 /* 101 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page 102 * protection for execute, and considers it the same as a read. Also, write 103 * permission implies read permission. This is the closest we can get.. 104 * 105 * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme, 106 * not only supporting separate execute, read, and write bits, but having 107 * completely separate permission bits for user and kernel space. 108 */ 109 /*xwr*/ 110 #define __P000 PAGE_NONE 111 #define __P001 PAGE_READONLY 112 #define __P010 PAGE_COPY 113 #define __P011 PAGE_COPY 114 #define __P100 PAGE_EXECREAD 115 #define __P101 PAGE_EXECREAD 116 #define __P110 PAGE_COPY 117 #define __P111 PAGE_COPY 118 119 #define __S000 PAGE_NONE 120 #define __S001 PAGE_READONLY 121 #define __S010 PAGE_WRITEONLY 122 #define __S011 PAGE_SHARED 123 #define __S100 PAGE_EXECREAD 124 #define __S101 PAGE_EXECREAD 125 #define __S110 PAGE_RWX 126 #define __S111 PAGE_RWX 127 128 typedef pte_t *pte_addr_t; 129 130 #define kern_addr_valid(addr) (1) 131 132 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ 133 remap_pfn_range(vma, vaddr, pfn, size, prot) 134 135 #define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT))) 136 137 /* 138 * No page table caches to initialise 139 */ 140 #define pgtable_cache_init() do { } while (0) 141 142 struct vm_area_struct; 143 144 extern void __update_cache(struct vm_area_struct *vma, 145 unsigned long address, pte_t pte); 146 extern void __update_tlb(struct vm_area_struct *vma, 147 unsigned long address, pte_t pte); 148 149 static inline void 150 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) 151 { 152 __update_cache(vma, address, pte); 153 __update_tlb(vma, address, pte); 154 } 155 156 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 157 extern void paging_init(void); 158 extern void page_table_range_init(unsigned long start, unsigned long end, 159 pgd_t *pgd); 160 161 /* arch/sh/mm/mmap.c */ 162 #define HAVE_ARCH_UNMAPPED_AREA 163 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 164 165 #include <asm-generic/pgtable.h> 166 167 #endif /* __ASM_SH_PGTABLE_H */ 168