1 #ifndef __ASM_SH_PCI_H 2 #define __ASM_SH_PCI_H 3 4 #ifdef __KERNEL__ 5 6 /* Can be used to override the logic in pci_scan_bus for skipping 7 already-configured bus numbers - to be used for buggy BIOSes 8 or architectures with incomplete PCI setup by the loader */ 9 10 #define pcibios_assign_all_busses() 1 11 12 /* 13 * A board can define one or more PCI channels that represent built-in (or 14 * external) PCI controllers. 15 */ 16 struct pci_channel { 17 struct pci_channel *next; 18 struct pci_bus *bus; 19 20 struct pci_ops *pci_ops; 21 22 struct resource *resources; 23 unsigned int nr_resources; 24 25 unsigned long io_offset; 26 unsigned long mem_offset; 27 28 unsigned long reg_base; 29 unsigned long io_map_base; 30 31 unsigned int index; 32 unsigned int need_domain_info; 33 34 /* Optional error handling */ 35 struct timer_list err_timer, serr_timer; 36 unsigned int err_irq, serr_irq; 37 }; 38 39 /* arch/sh/drivers/pci/pci.c */ 40 extern raw_spinlock_t pci_config_lock; 41 42 extern int register_pci_controller(struct pci_channel *hose); 43 extern void pcibios_report_status(unsigned int status_mask, int warn); 44 45 /* arch/sh/drivers/pci/common.c */ 46 extern int early_read_config_byte(struct pci_channel *hose, int top_bus, 47 int bus, int devfn, int offset, u8 *value); 48 extern int early_read_config_word(struct pci_channel *hose, int top_bus, 49 int bus, int devfn, int offset, u16 *value); 50 extern int early_read_config_dword(struct pci_channel *hose, int top_bus, 51 int bus, int devfn, int offset, u32 *value); 52 extern int early_write_config_byte(struct pci_channel *hose, int top_bus, 53 int bus, int devfn, int offset, u8 value); 54 extern int early_write_config_word(struct pci_channel *hose, int top_bus, 55 int bus, int devfn, int offset, u16 value); 56 extern int early_write_config_dword(struct pci_channel *hose, int top_bus, 57 int bus, int devfn, int offset, u32 value); 58 extern void pcibios_enable_timers(struct pci_channel *hose); 59 extern unsigned int pcibios_handle_status_errors(unsigned long addr, 60 unsigned int status, struct pci_channel *hose); 61 extern int pci_is_66mhz_capable(struct pci_channel *hose, 62 int top_bus, int current_bus); 63 64 extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM; 65 66 struct pci_dev; 67 68 #define HAVE_PCI_MMAP 69 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 70 enum pci_mmap_state mmap_state, int write_combine); 71 extern void pcibios_set_master(struct pci_dev *dev); 72 73 /* Dynamic DMA mapping stuff. 74 * SuperH has everything mapped statically like x86. 75 */ 76 77 /* The PCI address space does equal the physical memory 78 * address space. The networking and block device layers use 79 * this boolean for bounce buffer decisions. 80 */ 81 #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys) 82 83 #ifdef CONFIG_PCI 84 /* 85 * None of the SH PCI controllers support MWI, it is always treated as a 86 * direct memory write. 87 */ 88 #define PCI_DISABLE_MWI 89 #endif 90 91 /* Board-specific fixup routines. */ 92 int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin); 93 94 #define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index 95 96 static inline int pci_proc_domain(struct pci_bus *bus) 97 { 98 struct pci_channel *hose = bus->sysdata; 99 return hose->need_domain_info; 100 } 101 102 /* Chances are this interrupt is wired PC-style ... */ 103 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 104 { 105 return channel ? 15 : 14; 106 } 107 108 #endif /* __KERNEL__ */ 109 #endif /* __ASM_SH_PCI_H */ 110 111