1 /* 2 * Copyright (C) 1999 Niibe Yutaka 3 * Copyright (C) 2003 - 2007 Paul Mundt 4 * 5 * ASID handling idea taken from MIPS implementation. 6 */ 7 #ifndef __ASM_SH_MMU_CONTEXT_H 8 #define __ASM_SH_MMU_CONTEXT_H 9 10 #ifdef __KERNEL__ 11 #include <cpu/mmu_context.h> 12 #include <asm/tlbflush.h> 13 #include <linux/uaccess.h> 14 #include <linux/mm_types.h> 15 16 #include <asm/io.h> 17 #include <asm-generic/mm_hooks.h> 18 19 /* 20 * The MMU "context" consists of two things: 21 * (a) TLB cache version (or round, cycle whatever expression you like) 22 * (b) ASID (Address Space IDentifier) 23 */ 24 #ifdef CONFIG_CPU_HAS_PTEAEX 25 #define MMU_CONTEXT_ASID_MASK 0x0000ffff 26 #else 27 #define MMU_CONTEXT_ASID_MASK 0x000000ff 28 #endif 29 30 #define MMU_CONTEXT_VERSION_MASK (~0UL & ~MMU_CONTEXT_ASID_MASK) 31 #define MMU_CONTEXT_FIRST_VERSION (MMU_CONTEXT_ASID_MASK + 1) 32 33 /* Impossible ASID value, to differentiate from NO_CONTEXT. */ 34 #define MMU_NO_ASID MMU_CONTEXT_FIRST_VERSION 35 #define NO_CONTEXT 0UL 36 37 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 38 39 #ifdef CONFIG_MMU 40 #define cpu_context(cpu, mm) ((mm)->context.id[cpu]) 41 42 #define cpu_asid(cpu, mm) \ 43 (cpu_context((cpu), (mm)) & MMU_CONTEXT_ASID_MASK) 44 45 /* 46 * Virtual Page Number mask 47 */ 48 #define MMU_VPN_MASK 0xfffff000 49 50 #if defined(CONFIG_SUPERH32) 51 #include <asm/mmu_context_32.h> 52 #else 53 #include <asm/mmu_context_64.h> 54 #endif 55 56 /* 57 * Get MMU context if needed. 58 */ 59 static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu) 60 { 61 unsigned long asid = asid_cache(cpu); 62 63 /* Check if we have old version of context. */ 64 if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0) 65 /* It's up to date, do nothing */ 66 return; 67 68 /* It's old, we need to get new context with new version. */ 69 if (!(++asid & MMU_CONTEXT_ASID_MASK)) { 70 /* 71 * We exhaust ASID of this version. 72 * Flush all TLB and start new cycle. 73 */ 74 local_flush_tlb_all(); 75 76 #ifdef CONFIG_SUPERH64 77 /* 78 * The SH-5 cache uses the ASIDs, requiring both the I and D 79 * cache to be flushed when the ASID is exhausted. Weak. 80 */ 81 flush_cache_all(); 82 #endif 83 84 /* 85 * Fix version; Note that we avoid version #0 86 * to distinguish NO_CONTEXT. 87 */ 88 if (!asid) 89 asid = MMU_CONTEXT_FIRST_VERSION; 90 } 91 92 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 93 } 94 95 /* 96 * Initialize the context related info for a new mm_struct 97 * instance. 98 */ 99 static inline int init_new_context(struct task_struct *tsk, 100 struct mm_struct *mm) 101 { 102 int i; 103 104 for_each_online_cpu(i) 105 cpu_context(i, mm) = NO_CONTEXT; 106 107 return 0; 108 } 109 110 /* 111 * After we have set current->mm to a new value, this activates 112 * the context for the new mm so we see the new mappings. 113 */ 114 static inline void activate_context(struct mm_struct *mm, unsigned int cpu) 115 { 116 get_mmu_context(mm, cpu); 117 set_asid(cpu_asid(cpu, mm)); 118 } 119 120 static inline void switch_mm(struct mm_struct *prev, 121 struct mm_struct *next, 122 struct task_struct *tsk) 123 { 124 unsigned int cpu = smp_processor_id(); 125 126 if (likely(prev != next)) { 127 cpumask_set_cpu(cpu, mm_cpumask(next)); 128 set_TTB(next->pgd); 129 activate_context(next, cpu); 130 } else 131 if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next))) 132 activate_context(next, cpu); 133 } 134 135 #define activate_mm(prev, next) switch_mm((prev),(next),NULL) 136 #define deactivate_mm(tsk,mm) do { } while (0) 137 #define enter_lazy_tlb(mm,tsk) do { } while (0) 138 139 #else 140 141 #define set_asid(asid) do { } while (0) 142 #define get_asid() (0) 143 #define cpu_asid(cpu, mm) ({ (void)cpu; NO_CONTEXT; }) 144 #define switch_and_save_asid(asid) (0) 145 #define set_TTB(pgd) do { } while (0) 146 #define get_TTB() (0) 147 148 #include <asm-generic/mmu_context.h> 149 150 #endif /* CONFIG_MMU */ 151 152 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4) 153 /* 154 * If this processor has an MMU, we need methods to turn it off/on .. 155 * paging_init() will also have to be updated for the processor in 156 * question. 157 */ 158 static inline void enable_mmu(void) 159 { 160 unsigned int cpu = smp_processor_id(); 161 162 /* Enable MMU */ 163 __raw_writel(MMU_CONTROL_INIT, MMUCR); 164 ctrl_barrier(); 165 166 if (asid_cache(cpu) == NO_CONTEXT) 167 asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION; 168 169 set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK); 170 } 171 172 static inline void disable_mmu(void) 173 { 174 unsigned long cr; 175 176 cr = __raw_readl(MMUCR); 177 cr &= ~MMU_CONTROL_INIT; 178 __raw_writel(cr, MMUCR); 179 180 ctrl_barrier(); 181 } 182 #else 183 /* 184 * MMU control handlers for processors lacking memory 185 * management hardware. 186 */ 187 #define enable_mmu() do { } while (0) 188 #define disable_mmu() do { } while (0) 189 #endif 190 191 #endif /* __KERNEL__ */ 192 #endif /* __ASM_SH_MMU_CONTEXT_H */ 193