1 #ifndef __ASM_SH_IRQ_H 2 #define __ASM_SH_IRQ_H 3 4 #include <asm/machvec.h> 5 6 /* 7 * A sane default based on a reasonable vector table size, platforms are 8 * advised to cap this at the hard limit that they're interested in 9 * through the machvec. 10 */ 11 #define NR_IRQS 256 12 13 /* 14 * Convert back and forth between INTEVT and IRQ values. 15 */ 16 #ifdef CONFIG_CPU_HAS_INTEVT 17 #define evt2irq(evt) (((evt) >> 5) - 16) 18 #define irq2evt(irq) (((irq) + 16) << 5) 19 #else 20 #define evt2irq(evt) (evt) 21 #define irq2evt(irq) (irq) 22 #endif 23 24 /* 25 * Simple Mask Register Support 26 */ 27 extern void make_maskreg_irq(unsigned int irq); 28 extern unsigned short *irq_mask_register; 29 30 /* 31 * PINT IRQs 32 */ 33 void init_IRQ_pint(void); 34 void make_imask_irq(unsigned int irq); 35 36 static inline int generic_irq_demux(int irq) 37 { 38 return irq; 39 } 40 41 #define irq_canonicalize(irq) (irq) 42 #define irq_demux(irq) sh_mv.mv_irq_demux(irq) 43 44 #ifdef CONFIG_IRQSTACKS 45 extern void irq_ctx_init(int cpu); 46 extern void irq_ctx_exit(int cpu); 47 # define __ARCH_HAS_DO_SOFTIRQ 48 #else 49 # define irq_ctx_init(cpu) do { } while (0) 50 # define irq_ctx_exit(cpu) do { } while (0) 51 #endif 52 53 #ifdef CONFIG_CPU_SH5 54 #include <cpu/irq.h> 55 #endif 56 57 #endif /* __ASM_SH_IRQ_H */ 58