1f15cbe6fSPaul Mundt #ifndef __ASM_SH_HD64461 2f15cbe6fSPaul Mundt #define __ASM_SH_HD64461 3f15cbe6fSPaul Mundt /* 4f15cbe6fSPaul Mundt * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> 5f15cbe6fSPaul Mundt * Copyright (C) 2004 Paul Mundt 6f15cbe6fSPaul Mundt * Copyright (C) 2000 YAEGASHI Takeshi 7f15cbe6fSPaul Mundt * 8f15cbe6fSPaul Mundt * Hitachi HD64461 companion chip support 9f15cbe6fSPaul Mundt * (please note manual reference 0x10000000 = 0xb0000000) 10f15cbe6fSPaul Mundt */ 11f15cbe6fSPaul Mundt 12f15cbe6fSPaul Mundt /* Constants for PCMCIA mappings */ 13f15cbe6fSPaul Mundt #define HD64461_PCC_WINDOW 0x01000000 14f15cbe6fSPaul Mundt 15f15cbe6fSPaul Mundt /* Area 6 - Slot 0 - memory and/or IO card */ 16f15cbe6fSPaul Mundt #define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000) 17f15cbe6fSPaul Mundt #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */ 18f15cbe6fSPaul Mundt #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */ 19f15cbe6fSPaul Mundt #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */ 20f15cbe6fSPaul Mundt 21f15cbe6fSPaul Mundt /* Area 5 - Slot 1 - memory card only */ 22f15cbe6fSPaul Mundt #define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000) 23f15cbe6fSPaul Mundt #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */ 24f15cbe6fSPaul Mundt #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */ 25f15cbe6fSPaul Mundt 26f15cbe6fSPaul Mundt /* Standby Control Register for HD64461 */ 27f15cbe6fSPaul Mundt #define HD64461_STBCR CONFIG_HD64461_IOBASE 28f15cbe6fSPaul Mundt #define HD64461_STBCR_CKIO_STBY 0x2000 29f15cbe6fSPaul Mundt #define HD64461_STBCR_SAFECKE_IST 0x1000 30f15cbe6fSPaul Mundt #define HD64461_STBCR_SLCKE_IST 0x0800 31f15cbe6fSPaul Mundt #define HD64461_STBCR_SAFECKE_OST 0x0400 32f15cbe6fSPaul Mundt #define HD64461_STBCR_SLCKE_OST 0x0200 33f15cbe6fSPaul Mundt #define HD64461_STBCR_SMIAST 0x0100 34f15cbe6fSPaul Mundt #define HD64461_STBCR_SLCDST 0x0080 35f15cbe6fSPaul Mundt #define HD64461_STBCR_SPC0ST 0x0040 36f15cbe6fSPaul Mundt #define HD64461_STBCR_SPC1ST 0x0020 37f15cbe6fSPaul Mundt #define HD64461_STBCR_SAFEST 0x0010 38f15cbe6fSPaul Mundt #define HD64461_STBCR_STM0ST 0x0008 39f15cbe6fSPaul Mundt #define HD64461_STBCR_STM1ST 0x0004 40f15cbe6fSPaul Mundt #define HD64461_STBCR_SIRST 0x0002 41f15cbe6fSPaul Mundt #define HD64461_STBCR_SURTST 0x0001 42f15cbe6fSPaul Mundt 43f15cbe6fSPaul Mundt /* System Configuration Register */ 44f15cbe6fSPaul Mundt #define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02) 45f15cbe6fSPaul Mundt 46f15cbe6fSPaul Mundt /* CPU Data Bus Control Register */ 47f15cbe6fSPaul Mundt #define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04) 48f15cbe6fSPaul Mundt 49f15cbe6fSPaul Mundt /* Base Address Register */ 50f15cbe6fSPaul Mundt #define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000) 51f15cbe6fSPaul Mundt 52f15cbe6fSPaul Mundt /* Line increment address */ 53f15cbe6fSPaul Mundt #define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002) 54f15cbe6fSPaul Mundt 55f15cbe6fSPaul Mundt /* Controls LCD controller */ 56f15cbe6fSPaul Mundt #define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004) 57f15cbe6fSPaul Mundt 58f15cbe6fSPaul Mundt /* LCCDR control bits */ 59f15cbe6fSPaul Mundt #define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */ 60f15cbe6fSPaul Mundt #define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */ 61f15cbe6fSPaul Mundt #define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */ 62f15cbe6fSPaul Mundt #define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */ 63f15cbe6fSPaul Mundt #define HD64461_LCDCCR_EPON 0x0020 /* End Power On */ 64f15cbe6fSPaul Mundt #define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */ 65f15cbe6fSPaul Mundt 66f15cbe6fSPaul Mundt /* Controls LCD (1) */ 67f15cbe6fSPaul Mundt #define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010) 68f15cbe6fSPaul Mundt #define HD64461_LDR1_DON 0x01 /* Display On */ 69f15cbe6fSPaul Mundt #define HD64461_LDR1_DINV 0x80 /* Display Invert */ 70f15cbe6fSPaul Mundt 71f15cbe6fSPaul Mundt /* Controls LCD (2) */ 72f15cbe6fSPaul Mundt #define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012) 73f15cbe6fSPaul Mundt #define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */ 74f15cbe6fSPaul Mundt #define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */ 75f15cbe6fSPaul Mundt #define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */ 76f15cbe6fSPaul Mundt #define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */ 77f15cbe6fSPaul Mundt #define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */ 78f15cbe6fSPaul Mundt 79f15cbe6fSPaul Mundt /* Controls LCD (3) */ 80f15cbe6fSPaul Mundt #define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e) 81f15cbe6fSPaul Mundt 82f15cbe6fSPaul Mundt /* Palette Registers */ 83f15cbe6fSPaul Mundt #define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Address Register */ 84f15cbe6fSPaul Mundt #define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */ 85f15cbe6fSPaul Mundt #define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Address Register */ 86f15cbe6fSPaul Mundt #define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */ 87f15cbe6fSPaul Mundt 88f15cbe6fSPaul Mundt #define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */ 89f15cbe6fSPaul Mundt #define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */ 90f15cbe6fSPaul Mundt #define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */ 91f15cbe6fSPaul Mundt 92f15cbe6fSPaul Mundt #define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */ 93f15cbe6fSPaul Mundt #define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */ 94f15cbe6fSPaul Mundt #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */ 95f15cbe6fSPaul Mundt #define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */ 96f15cbe6fSPaul Mundt #define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */ 97f15cbe6fSPaul Mundt #define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ 98f15cbe6fSPaul Mundt 99f15cbe6fSPaul Mundt /* Line Drawing Registers */ 100f15cbe6fSPaul Mundt #define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Address Register (H) */ 101f15cbe6fSPaul Mundt #define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Address Register (L) */ 102f15cbe6fSPaul Mundt #define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */ 103f15cbe6fSPaul Mundt #define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */ 104f15cbe6fSPaul Mundt #define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */ 105f15cbe6fSPaul Mundt #define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */ 106f15cbe6fSPaul Mundt #define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */ 107f15cbe6fSPaul Mundt 108f15cbe6fSPaul Mundt /* BitBLT Registers */ 109f15cbe6fSPaul Mundt #define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Address Register (H) */ 110f15cbe6fSPaul Mundt #define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Address Register (L) */ 111f15cbe6fSPaul Mundt #define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Address Register (H) */ 112f15cbe6fSPaul Mundt #define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Address Register (L) */ 113f15cbe6fSPaul Mundt #define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */ 114f15cbe6fSPaul Mundt #define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */ 115f15cbe6fSPaul Mundt #define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Address Register (H) */ 116f15cbe6fSPaul Mundt #define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Address Register (L) */ 117f15cbe6fSPaul Mundt #define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Address Register (H) */ 118f15cbe6fSPaul Mundt #define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Address Register (L) */ 119f15cbe6fSPaul Mundt #define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */ 120f15cbe6fSPaul Mundt #define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */ 121f15cbe6fSPaul Mundt 122f15cbe6fSPaul Mundt /* PC Card Controller Registers */ 123f15cbe6fSPaul Mundt /* Maps to Physical Area 6 */ 124f15cbe6fSPaul Mundt #define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */ 125f15cbe6fSPaul Mundt #define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */ 126f15cbe6fSPaul Mundt #define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */ 127f15cbe6fSPaul Mundt #define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */ 128f15cbe6fSPaul Mundt #define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */ 129f15cbe6fSPaul Mundt /* Maps to Physical Area 5 */ 130f15cbe6fSPaul Mundt #define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */ 131f15cbe6fSPaul Mundt #define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */ 132f15cbe6fSPaul Mundt #define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */ 133f15cbe6fSPaul Mundt #define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */ 134f15cbe6fSPaul Mundt #define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */ 135f15cbe6fSPaul Mundt 136f15cbe6fSPaul Mundt /* PCC Interface Status Register */ 137f15cbe6fSPaul Mundt #define HD64461_PCCISR_READY 0x80 /* card ready */ 138f15cbe6fSPaul Mundt #define HD64461_PCCISR_MWP 0x40 /* card write-protected */ 139f15cbe6fSPaul Mundt #define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ 140f15cbe6fSPaul Mundt #define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ 141f15cbe6fSPaul Mundt #define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ 142f15cbe6fSPaul Mundt #define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ 143f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ 144f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ 145f15cbe6fSPaul Mundt 146f15cbe6fSPaul Mundt #define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ 147f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ 148f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ 149f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ 150f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ 151f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ 152f15cbe6fSPaul Mundt 153f15cbe6fSPaul Mundt /* PCC General Control Register */ 154f15cbe6fSPaul Mundt #define HD64461_PCCGCR_DRVE 0x80 /* output drive */ 155f15cbe6fSPaul Mundt #define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ 156f15cbe6fSPaul Mundt #define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ 157f15cbe6fSPaul Mundt #define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ 158f15cbe6fSPaul Mundt #define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ 159f15cbe6fSPaul Mundt #define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ 160f15cbe6fSPaul Mundt #define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ 161f15cbe6fSPaul Mundt #define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ 162f15cbe6fSPaul Mundt 163f15cbe6fSPaul Mundt /* PCC Card Status Change Register */ 164f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ 165f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ 166f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ 167f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ 168f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ 169f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_RC 0x04 /* READY change */ 170f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ 171f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ 172f15cbe6fSPaul Mundt 173f15cbe6fSPaul Mundt /* PCC Card Status Change Interrupt Enable Register */ 174f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ 175f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ 176f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ 177f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ 178f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ 179f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ 180f15cbe6fSPaul Mundt 181f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ 182f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ 183f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ 184f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ 185f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ 186f15cbe6fSPaul Mundt 187f15cbe6fSPaul Mundt /* PCC Software Control Register */ 188f15cbe6fSPaul Mundt #define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ 189f15cbe6fSPaul Mundt #define HD64461_PCCSCR_SWP 0x01 /* write protect */ 190f15cbe6fSPaul Mundt 191f15cbe6fSPaul Mundt /* PCC0 Output Pins Control Register */ 192f15cbe6fSPaul Mundt #define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a) 193f15cbe6fSPaul Mundt 194f15cbe6fSPaul Mundt /* PCC1 Output Pins Control Register */ 195f15cbe6fSPaul Mundt #define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c) 196f15cbe6fSPaul Mundt 197f15cbe6fSPaul Mundt /* PC Card General Control Register */ 198f15cbe6fSPaul Mundt #define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e) 199f15cbe6fSPaul Mundt 200f15cbe6fSPaul Mundt /* Port Control Registers */ 201f15cbe6fSPaul Mundt #define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */ 202f15cbe6fSPaul Mundt #define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */ 203f15cbe6fSPaul Mundt #define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */ 204f15cbe6fSPaul Mundt #define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */ 205f15cbe6fSPaul Mundt 206f15cbe6fSPaul Mundt /* Port Control Data Registers */ 207f15cbe6fSPaul Mundt #define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */ 208f15cbe6fSPaul Mundt #define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */ 209f15cbe6fSPaul Mundt #define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */ 210f15cbe6fSPaul Mundt #define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */ 211f15cbe6fSPaul Mundt 212f15cbe6fSPaul Mundt /* Interrupt Control Registers */ 213f15cbe6fSPaul Mundt #define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */ 214f15cbe6fSPaul Mundt #define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */ 215f15cbe6fSPaul Mundt #define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */ 216f15cbe6fSPaul Mundt #define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */ 217f15cbe6fSPaul Mundt 218f15cbe6fSPaul Mundt /* Interrupt Status Registers */ 219f15cbe6fSPaul Mundt #define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */ 220f15cbe6fSPaul Mundt #define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */ 221f15cbe6fSPaul Mundt #define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */ 222f15cbe6fSPaul Mundt #define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */ 223f15cbe6fSPaul Mundt 224f15cbe6fSPaul Mundt /* Interrupt Request Register & Interrupt Mask Register */ 225f15cbe6fSPaul Mundt #define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000) 226f15cbe6fSPaul Mundt #define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002) 227f15cbe6fSPaul Mundt 228f15cbe6fSPaul Mundt #define HD64461_IRQBASE OFFCHIP_IRQ_BASE 229f15cbe6fSPaul Mundt #define OFFCHIP_IRQ_BASE 64 230f15cbe6fSPaul Mundt #define HD64461_IRQ_NUM 16 231f15cbe6fSPaul Mundt 232f15cbe6fSPaul Mundt #define HD64461_IRQ_UART (HD64461_IRQBASE+5) 233f15cbe6fSPaul Mundt #define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) 234f15cbe6fSPaul Mundt #define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) 235f15cbe6fSPaul Mundt #define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) 236f15cbe6fSPaul Mundt #define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) 237f15cbe6fSPaul Mundt #define HD64461_IRQ_AFE (HD64461_IRQBASE+12) 238f15cbe6fSPaul Mundt #define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) 239f15cbe6fSPaul Mundt #define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) 240f15cbe6fSPaul Mundt 241f15cbe6fSPaul Mundt #define __IO_PREFIX hd64461 242f15cbe6fSPaul Mundt #include <asm/io_generic.h> 243f15cbe6fSPaul Mundt 244f15cbe6fSPaul Mundt /* arch/sh/cchips/hd6446x/hd64461/setup.c */ 245f15cbe6fSPaul Mundt int hd64461_irq_demux(int irq); 246f15cbe6fSPaul Mundt void hd64461_register_irq_demux(int irq, 247f15cbe6fSPaul Mundt int (*demux) (int irq, void *dev), void *dev); 248f15cbe6fSPaul Mundt void hd64461_unregister_irq_demux(int irq); 249f15cbe6fSPaul Mundt 250f15cbe6fSPaul Mundt #endif 251