1f15cbe6fSPaul Mundt #ifndef __ASM_SH_HD64461 2f15cbe6fSPaul Mundt #define __ASM_SH_HD64461 3f15cbe6fSPaul Mundt /* 4f15cbe6fSPaul Mundt * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> 5f15cbe6fSPaul Mundt * Copyright (C) 2004 Paul Mundt 6f15cbe6fSPaul Mundt * Copyright (C) 2000 YAEGASHI Takeshi 7f15cbe6fSPaul Mundt * 8f15cbe6fSPaul Mundt * Hitachi HD64461 companion chip support 9f15cbe6fSPaul Mundt * (please note manual reference 0x10000000 = 0xb0000000) 10f15cbe6fSPaul Mundt */ 11f15cbe6fSPaul Mundt 12f15cbe6fSPaul Mundt /* Constants for PCMCIA mappings */ 13f15cbe6fSPaul Mundt #define HD64461_PCC_WINDOW 0x01000000 14f15cbe6fSPaul Mundt 15f15cbe6fSPaul Mundt /* Area 6 - Slot 0 - memory and/or IO card */ 16bec36ecaSPaul Mundt #define HD64461_IOBASE 0xb0000000 17bec36ecaSPaul Mundt #define HD64461_IO_OFFSET(x) (HD64461_IOBASE + (x)) 18bec36ecaSPaul Mundt #define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000) 19f15cbe6fSPaul Mundt #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */ 20f15cbe6fSPaul Mundt #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */ 21f15cbe6fSPaul Mundt #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */ 22f15cbe6fSPaul Mundt 23f15cbe6fSPaul Mundt /* Area 5 - Slot 1 - memory card only */ 24bec36ecaSPaul Mundt #define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000) 25f15cbe6fSPaul Mundt #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */ 26f15cbe6fSPaul Mundt #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */ 27f15cbe6fSPaul Mundt 28f15cbe6fSPaul Mundt /* Standby Control Register for HD64461 */ 29f15cbe6fSPaul Mundt #define HD64461_STBCR CONFIG_HD64461_IOBASE 30f15cbe6fSPaul Mundt #define HD64461_STBCR_CKIO_STBY 0x2000 31f15cbe6fSPaul Mundt #define HD64461_STBCR_SAFECKE_IST 0x1000 32f15cbe6fSPaul Mundt #define HD64461_STBCR_SLCKE_IST 0x0800 33f15cbe6fSPaul Mundt #define HD64461_STBCR_SAFECKE_OST 0x0400 34f15cbe6fSPaul Mundt #define HD64461_STBCR_SLCKE_OST 0x0200 35f15cbe6fSPaul Mundt #define HD64461_STBCR_SMIAST 0x0100 36f15cbe6fSPaul Mundt #define HD64461_STBCR_SLCDST 0x0080 37f15cbe6fSPaul Mundt #define HD64461_STBCR_SPC0ST 0x0040 38f15cbe6fSPaul Mundt #define HD64461_STBCR_SPC1ST 0x0020 39f15cbe6fSPaul Mundt #define HD64461_STBCR_SAFEST 0x0010 40f15cbe6fSPaul Mundt #define HD64461_STBCR_STM0ST 0x0008 41f15cbe6fSPaul Mundt #define HD64461_STBCR_STM1ST 0x0004 42f15cbe6fSPaul Mundt #define HD64461_STBCR_SIRST 0x0002 43f15cbe6fSPaul Mundt #define HD64461_STBCR_SURTST 0x0001 44f15cbe6fSPaul Mundt 45f15cbe6fSPaul Mundt /* System Configuration Register */ 46bec36ecaSPaul Mundt #define HD64461_SYSCR HD64461_IO_OFFSET(0x02) 47f15cbe6fSPaul Mundt 48f15cbe6fSPaul Mundt /* CPU Data Bus Control Register */ 49bec36ecaSPaul Mundt #define HD64461_SCPUCR HD64461_IO_OFFSET(0x04) 50f15cbe6fSPaul Mundt 51f15cbe6fSPaul Mundt /* Base Address Register */ 52bec36ecaSPaul Mundt #define HD64461_LCDCBAR HD64461_IO_OFFSET(0x1000) 53f15cbe6fSPaul Mundt 54f15cbe6fSPaul Mundt /* Line increment address */ 55bec36ecaSPaul Mundt #define HD64461_LCDCLOR HD64461_IO_OFFSET(0x1002) 56f15cbe6fSPaul Mundt 57f15cbe6fSPaul Mundt /* Controls LCD controller */ 58bec36ecaSPaul Mundt #define HD64461_LCDCCR HD64461_IO_OFFSET(0x1004) 59f15cbe6fSPaul Mundt 60f15cbe6fSPaul Mundt /* LCCDR control bits */ 61f15cbe6fSPaul Mundt #define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */ 62f15cbe6fSPaul Mundt #define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */ 63f15cbe6fSPaul Mundt #define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */ 64f15cbe6fSPaul Mundt #define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */ 65f15cbe6fSPaul Mundt #define HD64461_LCDCCR_EPON 0x0020 /* End Power On */ 66f15cbe6fSPaul Mundt #define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */ 67f15cbe6fSPaul Mundt 68f15cbe6fSPaul Mundt /* Controls LCD (1) */ 69bec36ecaSPaul Mundt #define HD64461_LDR1 HD64461_IO_OFFSET(0x1010) 70f15cbe6fSPaul Mundt #define HD64461_LDR1_DON 0x01 /* Display On */ 71f15cbe6fSPaul Mundt #define HD64461_LDR1_DINV 0x80 /* Display Invert */ 72f15cbe6fSPaul Mundt 73f15cbe6fSPaul Mundt /* Controls LCD (2) */ 74bec36ecaSPaul Mundt #define HD64461_LDR2 HD64461_IO_OFFSET(0x1012) 75bec36ecaSPaul Mundt #define HD64461_LDHNCR HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */ 76bec36ecaSPaul Mundt #define HD64461_LDHNSR HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */ 77bec36ecaSPaul Mundt #define HD64461_LDVNTR HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */ 78bec36ecaSPaul Mundt #define HD64461_LDVNDR HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */ 79bec36ecaSPaul Mundt #define HD64461_LDVSPR HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */ 80f15cbe6fSPaul Mundt 81f15cbe6fSPaul Mundt /* Controls LCD (3) */ 82bec36ecaSPaul Mundt #define HD64461_LDR3 HD64461_IO_OFFSET(0x101e) 83f15cbe6fSPaul Mundt 84f15cbe6fSPaul Mundt /* Palette Registers */ 85bec36ecaSPaul Mundt #define HD64461_CPTWAR HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */ 86bec36ecaSPaul Mundt #define HD64461_CPTWDR HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */ 87bec36ecaSPaul Mundt #define HD64461_CPTRAR HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */ 88bec36ecaSPaul Mundt #define HD64461_CPTRDR HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */ 89f15cbe6fSPaul Mundt 90bec36ecaSPaul Mundt #define HD64461_GRDOR HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */ 91bec36ecaSPaul Mundt #define HD64461_GRSCR HD64461_IO_OFFSET(0x1042) /* Solid Color Register */ 92bec36ecaSPaul Mundt #define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */ 93f15cbe6fSPaul Mundt 94f15cbe6fSPaul Mundt #define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */ 95f15cbe6fSPaul Mundt #define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */ 96f15cbe6fSPaul Mundt #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */ 97f15cbe6fSPaul Mundt #define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */ 98f15cbe6fSPaul Mundt #define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */ 99f15cbe6fSPaul Mundt #define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ 100f15cbe6fSPaul Mundt 101f15cbe6fSPaul Mundt /* Line Drawing Registers */ 102bec36ecaSPaul Mundt #define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */ 103bec36ecaSPaul Mundt #define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */ 104bec36ecaSPaul Mundt #define HD64461_LNAXLR HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */ 105bec36ecaSPaul Mundt #define HD64461_LNDGR HD64461_IO_OFFSET(0x104c) /* Diagonal Register */ 106bec36ecaSPaul Mundt #define HD64461_LNAXR HD64461_IO_OFFSET(0x104e) /* Axial Register */ 107bec36ecaSPaul Mundt #define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */ 108bec36ecaSPaul Mundt #define HD64461_LNMDR HD64461_IO_OFFSET(0x1052) /* Line Mode Register */ 109f15cbe6fSPaul Mundt 110f15cbe6fSPaul Mundt /* BitBLT Registers */ 111bec36ecaSPaul Mundt #define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */ 112bec36ecaSPaul Mundt #define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */ 113bec36ecaSPaul Mundt #define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */ 114bec36ecaSPaul Mundt #define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */ 115bec36ecaSPaul Mundt #define HD64461_BBTDWR HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */ 116bec36ecaSPaul Mundt #define HD64461_BBTDHR HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */ 117bec36ecaSPaul Mundt #define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */ 118bec36ecaSPaul Mundt #define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */ 119bec36ecaSPaul Mundt #define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */ 120bec36ecaSPaul Mundt #define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */ 121bec36ecaSPaul Mundt #define HD64461_BBTROPR HD64461_IO_OFFSET(0x1068) /* ROP Register */ 122bec36ecaSPaul Mundt #define HD64461_BBTMDR HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */ 123f15cbe6fSPaul Mundt 124f15cbe6fSPaul Mundt /* PC Card Controller Registers */ 125f15cbe6fSPaul Mundt /* Maps to Physical Area 6 */ 126bec36ecaSPaul Mundt #define HD64461_PCC0ISR HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */ 127bec36ecaSPaul Mundt #define HD64461_PCC0GCR HD64461_IO_OFFSET(0x2002) /* socket 0 general control */ 128bec36ecaSPaul Mundt #define HD64461_PCC0CSCR HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */ 129bec36ecaSPaul Mundt #define HD64461_PCC0CSCIER HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */ 130bec36ecaSPaul Mundt #define HD64461_PCC0SCR HD64461_IO_OFFSET(0x2008) /* socket 0 software control */ 131f15cbe6fSPaul Mundt /* Maps to Physical Area 5 */ 132bec36ecaSPaul Mundt #define HD64461_PCC1ISR HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */ 133bec36ecaSPaul Mundt #define HD64461_PCC1GCR HD64461_IO_OFFSET(0x2012) /* socket 1 general control */ 134bec36ecaSPaul Mundt #define HD64461_PCC1CSCR HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */ 135bec36ecaSPaul Mundt #define HD64461_PCC1CSCIER HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */ 136bec36ecaSPaul Mundt #define HD64461_PCC1SCR HD64461_IO_OFFSET(0x2018) /* socket 1 software control */ 137f15cbe6fSPaul Mundt 138f15cbe6fSPaul Mundt /* PCC Interface Status Register */ 139f15cbe6fSPaul Mundt #define HD64461_PCCISR_READY 0x80 /* card ready */ 140f15cbe6fSPaul Mundt #define HD64461_PCCISR_MWP 0x40 /* card write-protected */ 141f15cbe6fSPaul Mundt #define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ 142f15cbe6fSPaul Mundt #define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ 143f15cbe6fSPaul Mundt #define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ 144f15cbe6fSPaul Mundt #define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ 145f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ 146f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ 147f15cbe6fSPaul Mundt 148f15cbe6fSPaul Mundt #define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ 149f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ 150f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ 151f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ 152f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ 153f15cbe6fSPaul Mundt #define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ 154f15cbe6fSPaul Mundt 155f15cbe6fSPaul Mundt /* PCC General Control Register */ 156f15cbe6fSPaul Mundt #define HD64461_PCCGCR_DRVE 0x80 /* output drive */ 157f15cbe6fSPaul Mundt #define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ 158f15cbe6fSPaul Mundt #define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ 159f15cbe6fSPaul Mundt #define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ 160f15cbe6fSPaul Mundt #define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ 161f15cbe6fSPaul Mundt #define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ 162f15cbe6fSPaul Mundt #define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ 163f15cbe6fSPaul Mundt #define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ 164f15cbe6fSPaul Mundt 165f15cbe6fSPaul Mundt /* PCC Card Status Change Register */ 166f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ 167f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ 168f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ 169f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ 170f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ 171f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_RC 0x04 /* READY change */ 172f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ 173f15cbe6fSPaul Mundt #define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ 174f15cbe6fSPaul Mundt 175f15cbe6fSPaul Mundt /* PCC Card Status Change Interrupt Enable Register */ 176f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ 177f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ 178f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ 179f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ 180f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ 181f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ 182f15cbe6fSPaul Mundt 183f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ 184f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ 185f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ 186f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ 187f15cbe6fSPaul Mundt #define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ 188f15cbe6fSPaul Mundt 189f15cbe6fSPaul Mundt /* PCC Software Control Register */ 190f15cbe6fSPaul Mundt #define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ 191f15cbe6fSPaul Mundt #define HD64461_PCCSCR_SWP 0x01 /* write protect */ 192f15cbe6fSPaul Mundt 193f15cbe6fSPaul Mundt /* PCC0 Output Pins Control Register */ 194bec36ecaSPaul Mundt #define HD64461_P0OCR HD64461_IO_OFFSET(0x202a) 195f15cbe6fSPaul Mundt 196f15cbe6fSPaul Mundt /* PCC1 Output Pins Control Register */ 197bec36ecaSPaul Mundt #define HD64461_P1OCR HD64461_IO_OFFSET(0x202c) 198f15cbe6fSPaul Mundt 199f15cbe6fSPaul Mundt /* PC Card General Control Register */ 200bec36ecaSPaul Mundt #define HD64461_PGCR HD64461_IO_OFFSET(0x202e) 201f15cbe6fSPaul Mundt 202f15cbe6fSPaul Mundt /* Port Control Registers */ 203bec36ecaSPaul Mundt #define HD64461_GPACR HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */ 204bec36ecaSPaul Mundt #define HD64461_GPBCR HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */ 205bec36ecaSPaul Mundt #define HD64461_GPCCR HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */ 206bec36ecaSPaul Mundt #define HD64461_GPDCR HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */ 207f15cbe6fSPaul Mundt 208f15cbe6fSPaul Mundt /* Port Control Data Registers */ 209bec36ecaSPaul Mundt #define HD64461_GPADR HD64461_IO_OFFSET(0x4010) /* A */ 210bec36ecaSPaul Mundt #define HD64461_GPBDR HD64461_IO_OFFSET(0x4012) /* B */ 211bec36ecaSPaul Mundt #define HD64461_GPCDR HD64461_IO_OFFSET(0x4014) /* C */ 212bec36ecaSPaul Mundt #define HD64461_GPDDR HD64461_IO_OFFSET(0x4016) /* D */ 213f15cbe6fSPaul Mundt 214f15cbe6fSPaul Mundt /* Interrupt Control Registers */ 215bec36ecaSPaul Mundt #define HD64461_GPAICR HD64461_IO_OFFSET(0x4020) /* A */ 216bec36ecaSPaul Mundt #define HD64461_GPBICR HD64461_IO_OFFSET(0x4022) /* B */ 217bec36ecaSPaul Mundt #define HD64461_GPCICR HD64461_IO_OFFSET(0x4024) /* C */ 218bec36ecaSPaul Mundt #define HD64461_GPDICR HD64461_IO_OFFSET(0x4026) /* D */ 219f15cbe6fSPaul Mundt 220f15cbe6fSPaul Mundt /* Interrupt Status Registers */ 221bec36ecaSPaul Mundt #define HD64461_GPAISR HD64461_IO_OFFSET(0x4040) /* A */ 222bec36ecaSPaul Mundt #define HD64461_GPBISR HD64461_IO_OFFSET(0x4042) /* B */ 223bec36ecaSPaul Mundt #define HD64461_GPCISR HD64461_IO_OFFSET(0x4044) /* C */ 224bec36ecaSPaul Mundt #define HD64461_GPDISR HD64461_IO_OFFSET(0x4046) /* D */ 225f15cbe6fSPaul Mundt 226f15cbe6fSPaul Mundt /* Interrupt Request Register & Interrupt Mask Register */ 227bec36ecaSPaul Mundt #define HD64461_NIRR HD64461_IO_OFFSET(0x5000) 228bec36ecaSPaul Mundt #define HD64461_NIMR HD64461_IO_OFFSET(0x5002) 229f15cbe6fSPaul Mundt 230f15cbe6fSPaul Mundt #define HD64461_IRQBASE OFFCHIP_IRQ_BASE 231f15cbe6fSPaul Mundt #define OFFCHIP_IRQ_BASE 64 232f15cbe6fSPaul Mundt #define HD64461_IRQ_NUM 16 233f15cbe6fSPaul Mundt 234f15cbe6fSPaul Mundt #define HD64461_IRQ_UART (HD64461_IRQBASE+5) 235f15cbe6fSPaul Mundt #define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) 236f15cbe6fSPaul Mundt #define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) 237f15cbe6fSPaul Mundt #define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) 238f15cbe6fSPaul Mundt #define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) 239f15cbe6fSPaul Mundt #define HD64461_IRQ_AFE (HD64461_IRQBASE+12) 240f15cbe6fSPaul Mundt #define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) 241f15cbe6fSPaul Mundt #define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) 242f15cbe6fSPaul Mundt 243f15cbe6fSPaul Mundt #define __IO_PREFIX hd64461 244f15cbe6fSPaul Mundt #include <asm/io_generic.h> 245f15cbe6fSPaul Mundt 246f15cbe6fSPaul Mundt /* arch/sh/cchips/hd6446x/hd64461/setup.c */ 247f15cbe6fSPaul Mundt void hd64461_register_irq_demux(int irq, 248f15cbe6fSPaul Mundt int (*demux) (int irq, void *dev), void *dev); 249f15cbe6fSPaul Mundt void hd64461_unregister_irq_demux(int irq); 250f15cbe6fSPaul Mundt 251f15cbe6fSPaul Mundt #endif 252