1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2e839ca52SDavid Howells /* 3e839ca52SDavid Howells * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima 4e839ca52SDavid Howells * Copyright (C) 2002 Paul Mundt 5e839ca52SDavid Howells */ 6e839ca52SDavid Howells #ifndef __ASM_SH_BARRIER_H 7e839ca52SDavid Howells #define __ASM_SH_BARRIER_H 8e839ca52SDavid Howells 937744feeSArnd Bergmann #if defined(CONFIG_CPU_SH4A) 10e839ca52SDavid Howells #include <asm/cache_insns.h> 11e839ca52SDavid Howells #endif 12e839ca52SDavid Howells 13e839ca52SDavid Howells /* 14e839ca52SDavid Howells * A brief note on ctrl_barrier(), the control register write barrier. 15e839ca52SDavid Howells * 16e839ca52SDavid Howells * Legacy SH cores typically require a sequence of 8 nops after 17e839ca52SDavid Howells * modification of a control register in order for the changes to take 18e839ca52SDavid Howells * effect. On newer cores (like the sh4a and sh5) this is accomplished 19e839ca52SDavid Howells * with icbi. 20e839ca52SDavid Howells * 21e839ca52SDavid Howells * Also note that on sh4a in the icbi case we can forego a synco for the 22e839ca52SDavid Howells * write barrier, as it's not necessary for control registers. 23e839ca52SDavid Howells * 24e839ca52SDavid Howells * Historically we have only done this type of barrier for the MMUCR, but 25e839ca52SDavid Howells * it's also necessary for the CCR, so we make it generic here instead. 26e839ca52SDavid Howells */ 2737744feeSArnd Bergmann #if defined(CONFIG_CPU_SH4A) 28e839ca52SDavid Howells #define mb() __asm__ __volatile__ ("synco": : :"memory") 29e839ca52SDavid Howells #define rmb() mb() 3093ea02bbSPeter Zijlstra #define wmb() mb() 31e839ca52SDavid Howells #define ctrl_barrier() __icbi(PAGE_OFFSET) 32e839ca52SDavid Howells #else 332b47d54eSRich Felker #if defined(CONFIG_CPU_J2) && defined(CONFIG_SMP) 342b47d54eSRich Felker #define __smp_mb() do { int tmp = 0; __asm__ __volatile__ ("cas.l %0,%0,@%1" : "+r"(tmp) : "z"(&tmp) : "memory", "t"); } while(0) 352b47d54eSRich Felker #define __smp_rmb() __smp_mb() 362b47d54eSRich Felker #define __smp_wmb() __smp_mb() 372b47d54eSRich Felker #endif 38e839ca52SDavid Howells #define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") 39e839ca52SDavid Howells #endif 40e839ca52SDavid Howells 4190a3ccb0SMichael S. Tsirkin #define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0) 42e839ca52SDavid Howells 4393ea02bbSPeter Zijlstra #include <asm-generic/barrier.h> 4493ea02bbSPeter Zijlstra 45e839ca52SDavid Howells #endif /* __ASM_SH_BARRIER_H */ 46