1 /* 2 * SH7786 PCI-Express controller definitions. 3 * 4 * Copyright (C) 2008, 2009 Renesas Technology Corp. 5 * All rights reserved. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #ifndef __PCI_SH7786_H 12 #define __PCI_SH7786_H 13 14 /* PCIe bus-0(x4) on SH7786 */ // Rev1.171 15 #define SH4A_PCIE_SPW_BASE 0xFE000000 /* spw config address for controller 0 */ 16 #define SH4A_PCIE_SPW_BASE1 0xFE200000 /* spw config address for controller 1 (Rev1.14)*/ 17 #define SH4A_PCIE_SPW_BASE2 0xFCC00000 /* spw config address for controller 2 (Rev1.171)*/ 18 #define SH4A_PCIE_SPW_BASE_LEN 0x00080000 19 20 #define SH4A_PCI_CNFG_BASE 0xFE040000 /* pci config address for controller 0 */ 21 #define SH4A_PCI_CNFG_BASE1 0xFE240000 /* pci config address for controller 1 (Rev1.14)*/ 22 #define SH4A_PCI_CNFG_BASE2 0xFCC40000 /* pci config address for controller 2 (Rev1.171)*/ 23 #define SH4A_PCI_CNFG_BASE_LEN 0x00040000 24 25 #define SH4A_PCIPIO_ADDR_OFFSET 0x000001c0 /* offset to pci config_address */ 26 #define SH4A_PCIPIO_DATA_OFFSET 0x00000220 /* offset to pci config_data */ 27 28 /* 29 * for PEX8111(Max Payload Size=128B,PCIIO_SIZE=64K), 30 * for other(Max Payload Size=4096B,PCIIO_SIZE=8M) 31 */ 32 33 /* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/ 34 #define SH4A_PCIBMSTR_TRANSLATION 0x20000000 35 36 /* SPVCR0 */ 37 #define SH4A_PCIEVCR0 (0x000000) /* R - 0x0000 0000 32 */ 38 #define BITS_TOP_MB (24) 39 #define MASK_TOP_MB (0xff<<BITS_TOP_MB) 40 #define BITS_BOT_MB (16) 41 #define MASK_BOT_MB (0xff<<BITS_BOT_MB) 42 #define BITS_VC_ID (0) 43 #define MASK_VC_ID (0xffff<<BITS_VC_ID) 44 45 /* SPVCR1 */ 46 #define SH4A_PCIEVCR1 (0x000004) /* R - 0x0000 0000 32*/ 47 #define BITS_BADOPC (5) /* 5 BADOPC 0 R/W */ 48 #define MASK_BADOPC (1<<BITS_BADOPC) 49 #define BITS_BADDEST (4) /*4 BADDEST 0 R/W */ 50 #define MASK_BADDEST (1<<BITS_BADDEST) 51 #define BITS_UNSOLRESP (3) /* 3 UNSOLRESP 0 R/W */ 52 #define MASK_UNSOLRESP (1<<BITS_UNSOLRESP) 53 #define BITS_ERRSNT (1) /* 1 ERRSNT 0 */ 54 #define MASK_ERRSNT (1<<BITS_ERRSNT) 55 #define BITS_ERRRCV (0) /* 0 ERRRCV 0 */ 56 #define MASK_ERRRCV (1<<BITS_ERRRCV) 57 58 /* PCIEENBLR */ 59 #define SH4A_PCIEENBLR (0x000008) /* R/W - 0x0000 0001 32 */ 60 61 /* PCIEECR */ 62 #define SH4A_PCIEECR (0x00000C) /* R/W - 0x0000 0000 32 */ 63 #define BITS_ENBL (0) /* 0 ENBL 0 R/W */ 64 #define MASK_ENBL (1<<BITS_ENBL) 65 66 /* PCIEPAR */ 67 #define SH4A_PCIEPAR (0x000010) /* R/W - 0x0000 0000 32 */ 68 #define BITS_BN (24) 69 #define MASK_BN (0xff<<BITS_BN) 70 #define BITS_DN (19) 71 #define MASK_DN (0x1f<<BITS_DN) 72 #define BITS_FN (16) 73 #define MASK_FN (0x7<<BITS_FN) 74 #define BITS_EREGNO (8) 75 #define MASK_EREGNO (0xff<<BITS_EREGNO) 76 #define BITS_REGNO (2) 77 #define MASK_REGNO (0x3f<<BITS_REGNO) 78 79 /* PCIEPCTLR */ 80 #define SH4A_PCIEPCTLR (0x000018) /* R/W - 0x0000 0000 32 */ 81 #define BITS_CCIE (31) /* 31 CCIE */ 82 #define MASK_CCIE (1<<BITS_CCIE) 83 #define BITS_TYPE (8) 84 #define MASK_TYPE (1<<BITS_TYPE) 85 #define BITS_C_VC (0) 86 #define MASK_C_VC (1<<BITS_C_VC) 87 88 /* PCIEPDR */ 89 #define SH4A_PCIEPDR (0x000020) /* R/W - 0x0000 0000 32 */ 90 #define BITS_PDR (0) 91 #define MASK_PDR (0xffffffff<<BITS_PDR) 92 93 /* PCIEMSGALR */ 94 #define SH4A_PCIEMSGALR (0x000030) /* R/W - 0x0000 0000 32 */ 95 #define BITS_MSGADRL (0) 96 #define MASK_MSGADRL (0xffffffff<<BITS_MSGADRL) 97 98 /* PCIEMSGAHR */ 99 #define SH4A_PCIEMSGAHR (0x000034) /* R/W - 0x0000 0000 32 */ 100 #define BITS_MSGADRH (0) 101 #define MASK_MSGADRH (0xffffffff<<BITS_MSGADRH) 102 103 /* PCIEMSGCTLR */ 104 #define SH4A_PCIEMSGCTLR (0x000038) /* R/W - 0x0000 0000 32 */ 105 #define BITS_MSGIE (31) 106 #define MASK_MSGIE (1<<BITS_MSGIE) 107 #define BITS_MROUTE (16) 108 #define MASK_MROUTE (0x7<<BITS_MROUTE) 109 #define BITS_MCODE (8) 110 #define MASK_MCODE (0xff<<BITS_MCODE) 111 #define BITS_M_VC (0) 112 #define MASK_M_VC (1<<BITS_M_VC) 113 114 /* PCIEMSG */ 115 #define SH4A_PCIEMSG (0x000040) /* W - - 32 */ 116 #define BITS_MDATA (0) 117 #define MASK_MDATA (0xffffffff<<BITS_MDATA) 118 119 /* PCIEUNLOCKCR */ 120 #define SH4A_PCIEUNLOCKCR (0x000048) /* R/W - 0x0000 0000 32 */ 121 122 /* PCIEIDR */ 123 #define SH4A_PCIEIDR (0x000060) /* R/W - 0x0101 1101 32 */ 124 125 /* PCIEDBGCTLR */ 126 #define SH4A_PCIEDBGCTLR (0x000100) /* R/W - 0x0000 0000 32 */ 127 128 /* PCIEINTXR */ 129 #define SH4A_PCIEINTXR (0x004000) /* R/W - 0x0000 0000 32 */ 130 131 /* PCIERMSGR */ 132 #define SH4A_PCIERMSGR (0x004010) /* R/W - 0x0000 0000 32 */ 133 134 /* PCIERSTR */ 135 #define SH4A_PCIERSTR(x) (0x008000 + ((x) * 0x4)) /* R/W - 0x0000 0000 32 */ 136 137 /* PCIESRSTR */ 138 #define SH4A_PCIESRSTR (0x008040) /* R/W - 0x0000 0000 32 */ 139 140 /* PCIEPHYCTLR */ 141 #define SH4A_PCIEPHYCTLR (0x010000) /* R/W - 0x0000 0000 32 */ 142 #define BITS_CKE (0) 143 #define MASK_CKE (1<<BITS_CKE) 144 145 /* PCIERMSGIER */ 146 #define SH4A_PCIERMSGIER (0x004040) /* R/W - 0x0000 0000 32 */ 147 148 /* PCIEPHYADRR */ 149 #define SH4A_PCIEPHYADRR (0x010004) /* R/W - 0x0000 0000 32 */ 150 #define BITS_ACK (24) // Rev1.171 151 #define MASK_ACK (1<<BITS_ACK) // Rev1.171 152 #define BITS_CMD (16) // Rev1.171 153 #define MASK_CMD (0x03<<BITS_CMD) // Rev1.171 154 #define BITS_LANE (8) 155 #define MASK_LANE (0x0f<<BITS_LANE) 156 #define BITS_ADR (0) 157 #define MASK_ADR (0xff<<BITS_ADR) 158 159 /* PCIEPHYDINR */ // Rev1.171 start. 160 #define SH4A_PCIEPHYDINR (0x010008) /* R/W - 0x0000 0000 32 */ 161 162 /* PCIEPHYDOUTR */ 163 #define SH4A_PCIEPHYDOUTR (0x01000C) /* R/W - 0x0000 0000 32 */ 164 165 /* PCIEPHYSR */ 166 #define SH4A_PCIEPHYSR (0x010010) /* R/W - 0x0000 0000 32 */ // Rev1.171 end. 167 168 /* PCIEPHYDATAR */ 169 #define SH4A_PCIEPHYDATAR (0x00008) /* R/W - 0xxxxx xxxx 32 */ 170 #define BITS_DATA (0) 171 #define MASK_DATA (0xffffffff<<BITS_DATA) 172 173 /* PCIETCTLR */ 174 #define SH4A_PCIETCTLR (0x020000) /* R/W R/W 0x0000 0000 32 */ 175 #define BITS_CFINT (0) 176 #define MASK_CFINT (1<<BITS_CFINT) 177 178 /* PCIETSTR */ 179 #define SH4A_PCIETSTR (0x020004) /* R 0x0000 0000 32 */ 180 181 /* PCIEINTR */ 182 #define SH4A_PCIEINTR (0x020008) /* R/W R/W 0x0000 0000 32 */ 183 #define BITS_INT_RX_ERP (31) 184 #define MASK_INT_RX_ERP (1<<BITS_INT_RX_ERP) 185 #define BITS_INT_RX_VCX_Posted (30) 186 #define MASK_INT_RX_VCX_Posted (1<<BITS_INT_RX_VCX_Posted) 187 #define BITS_INT_RX_VCX_NonPosted (29) 188 #define MASK_INT_RX_VCX_NonPosted (1<<BITS_INT_RX_VCX_NonPosted) 189 #define BITS_INT_RX_VCX_CPL (28) 190 #define MASK_INT_RX_VCX_CPL (1<<BITS_INT_RX_VCX_CPL) 191 #define BITS_INT_TX_VCX_Posted (26) 192 #define MASK_INT_TX_VCX_Posted (1<<BITS_INT_TX_VCX_Posted) 193 #define BITS_INT_TX_VCX_NonPosted (25) 194 #define MASK_INT_TX_VCX_NonPosted (1<<BITS_INT_TX_VCX_NonPosted) 195 #define BITS_INT_TX_VCX_CPL (24) 196 #define MASK_INT_TX_VCX_CPL (1<<BITS_INT_TX_VCX_CPL) 197 #define BITS_INT_RX_VC0_Posted (22) 198 #define MASK_INT_RX_VC0_Posted (1<<BITS_INT_RX_VC0_Posted) 199 #define BITS_INT_RX_VC0_NonPosted (21) 200 #define MASK_INT_RX_VC0_NonPosted (1<<BITS_INT_RX_VC0_NonPosted) 201 #define BITS_INT_RX_VC0_CPL (20) 202 #define MASK_INT_RX_VC0_CPL (1<<BITS_INT_RX_VC0_CPL) 203 #define BITS_INT_TX_VC0_Posted (18) 204 #define MASK_INT_TX_VC0_Posted (1<<BITS_INT_TX_VC0_Posted) 205 #define BITS_INT_TX_VC0_NonPosted (17) 206 #define MASK_INT_TX_VC0_NonPosted (1<<BITS_INT_TX_VC0_NonPosted) 207 #define BITS_INT_TX_VC0_CPL (16) 208 #define MASK_INT_TX_VC0_CPL (1<<BITS_INT_TX_VC0_CPL) 209 #define BITS_INT_RX_CTRL (15) 210 #define MASK_INT_RX_CTRL (1<<BITS_INT_RX_CTRL) 211 #define BITS_INT_TX_CTRL (14) 212 #define MASK_INT_TX_CTRL (1<<BITS_INT_TX_CTRL) 213 #define BITS_INTTL (11) 214 #define MASK_INTTL (1<<BITS_INTTL) 215 #define BITS_INTDL (10) 216 #define MASK_INTDL (1<<BITS_INTDL) 217 #define BITS_INTMAC (9) 218 #define MASK_INTMAC (1<<BITS_INTMAC) 219 #define BITS_INTPM (8) 220 #define MASK_INTPM (1<<BITS_INTPM) 221 222 /* PCIEINTER */ 223 #define SH4A_PCIEINTER (0x02000C) /* R/W R/W 0x0000 0000 32 */ 224 #define BITS_INT_RX_ERP (31) 225 #define MASK_INT_RX_ERP (1<<BITS_INT_RX_ERP) 226 #define BITS_INT_RX_VCX_Posted (30) 227 #define MASK_INT_RX_VCX_Posted (1<<BITS_INT_RX_VCX_Posted) 228 #define BITS_INT_RX_VCX_NonPosted (29) 229 #define MASK_INT_RX_VCX_NonPosted (1<<BITS_INT_RX_VCX_NonPosted) 230 #define BITS_INT_RX_VCX_CPL (28) 231 #define MASK_INT_RX_VCX_CPL (1<<BITS_INT_RX_VCX_CPL) 232 #define BITS_INT_TX_VCX_Posted (26) 233 #define MASK_INT_TX_VCX_Posted (1<<BITS_INT_TX_VCX_Posted) 234 #define BITS_INT_TX_VCX_NonPosted (25) 235 #define MASK_INT_TX_VCX_NonPosted (1<<BITS_INT_TX_VCX_NonPosted) 236 #define BITS_INT_TX_VCX_CPL (24) 237 #define MASK_INT_TX_VCX_CPL (1<<BITS_INT_TX_VCX_CPL) 238 #define BITS_INT_RX_VC0_Posted (22) 239 #define MASK_INT_RX_VC0_Posted (1<<BITS_INT_RX_VC0_Posted) 240 #define BITS_INT_RX_VC0_NonPosted (21) 241 #define MASK_INT_RX_VC0_NonPosted (1<<BITS_INT_RX_VC0_NonPosted) 242 #define BITS_INT_RX_VC0_CPL (20) 243 #define MASK_INT_RX_VC0_CPL (1<<BITS_INT_RX_VC0_CPL) 244 #define BITS_INT_TX_VC0_Posted (18) 245 #define MASK_INT_TX_VC0_Posted (1<<BITS_INT_TX_VC0_Posted) 246 #define BITS_INT_TX_VC0_NonPosted (17) 247 #define MASK_INT_TX_VC0_NonPosted (1<<BITS_INT_TX_VC0_NonPosted) 248 #define BITS_INT_TX_VC0_CPL (16) 249 #define MASK_INT_TX_VC0_CPL (1<<BITS_INT_TX_VC0_CPL) 250 #define BITS_INT_RX_CTRL (15) 251 #define MASK_INT_RX_CTRL (1<<BITS_INT_RX_CTRL) 252 #define BITS_INT_TX_CTRL (14) 253 #define MASK_INT_TX_CTRL (1<<BITS_INT_TX_CTRL) 254 #define BITS_INTTL (11) 255 #define MASK_INTTL (1<<BITS_INTTL) 256 #define BITS_INTDL (10) 257 #define MASK_INTDL (1<<BITS_INTDL) 258 #define BITS_INTMAC (9) 259 #define MASK_INTMAC (1<<BITS_INTMAC) 260 #define BITS_INTPM (8) 261 #define MASK_INTPM (1<<BITS_INTPM) 262 263 /* PCIEEH0R */ 264 #define SH4A_PCIEEHR(x) (0x020010 + ((x) * 0x4)) /* R - 0x0000 0000 32 */ 265 266 /* PCIEAIR */ 267 #define SH4A_PCIEAIR (SH4A_PCIE_BASE + 0x020010) /* R/W R/W 0xxxxx xxxx 32 */ 268 269 /* PCIECIR */ 270 #define SH4A_PCIECIR (SH4A_PCIE_BASE) /* R/W R/W 0xxxxx xxxx 32 */ 271 272 /* PCIEERRFR */ // Rev1.18 273 #define SH4A_PCIEERRFR (0x020020) /* R/W R/W 0xxxxx xxxx 32 */ // Rev1.18 274 275 /* PCIEERRFER */ 276 #define SH4A_PCIEERRFER (0x020024) /* R/W R/W 0x0000 0000 32 */ 277 278 /* PCIEERRFR2 */ 279 #define SH4A_PCIEERRFR2 (0x020028) /* R/W R/W 0x0000 0000 32 */ 280 281 /* PCIEMSIR */ 282 #define SH4A_PCIEMSIR (0x020040) /* R/W - 0x0000 0000 32 */ 283 284 /* PCIEMSIFR */ 285 #define SH4A_PCIEMSIFR (0x020044) /* R/W R/W 0x0000 0000 32 */ 286 287 /* PCIEPWRCTLR */ 288 #define SH4A_PCIEPWRCTLR (0x020100) /* R/W - 0x0000 0000 32 */ 289 290 /* PCIEPCCTLR */ 291 #define SH4A_PCIEPCCTLR (0x020180) /* R/W - 0x0000 0000 32 */ 292 293 // Rev1.18 294 /* PCIELAR0 */ 295 #define SH4A_PCIELAR0 (0x020200) /* R/W R/W 0x0000 0000 32 */ 296 #define BITS_LARn (20) 297 #define MASK_LARn (0xfff<<BITS_LARn) 298 299 #define SH4A_PCIE_020204 (0x020204) /* R/W R/W 0x0000 0000 32 */ 300 301 /* PCIELAMR0 */ 302 #define SH4A_PCIELAMR0 (0x020208) /* R/W R/W 0x0000 0000 32 */ 303 #define BITS_LAMRn (20) 304 #define MASK_LAMRn (0x1ff<<BITS_LAMRn) 305 #define BITS_LAREn (0) 306 #define MASK_LAREn (0x1<<BITS_LAREn) 307 308 /* PCIECSCR0 */ 309 #define SH4A_PCIECSCR0 (0x020210) /* R/W R/W 0x0000 0000 32 */ 310 #define BITS_RANGE (2) 311 #define MASK_RANGE (0x7<<BITS_RANGE) 312 #define BITS_SNPMD (0) 313 #define MASK_SNPMD (0x3<<BITS_SNPMD) 314 315 /* PCIECSAR0 */ 316 #define SH4A_PCIECSAR0 (0x020214) /* R/W R/W 0x0000 0000 32 */ 317 #define BITS_CSADR (0) 318 #define MASK_CSADR (0xffffffff<<BITS_CSADR) 319 320 /* PCIESTCTLR0 */ 321 #define SH4A_PCIESTCTLR0 (0x020218) /* R/W R/W 0x0000 0000 32 */ 322 #define BITS_SHPRI (8) 323 #define MASK_SHPRI (0x0f<<BITS_SHPRI) 324 325 #define SH4A_PCIE_020224 (0x020224) /* R/W R/W 0x0000 0000 32 */ 326 327 #define SH4A_PCIELAR1 (0x020220) /* R/W R/W 0x0000 0000 32 */ 328 #define SH4A_PCIELAMR1 (0x020228) /* R/W R/W 0x0000 0000 32 */ 329 #define SH4A_PCIECSCR1 (0x020230) /* R/W R/W 0x0000 0000 32 */ 330 #define SH4A_PCIECSAR1 (0x020234) /* R/W R/W 0x0000 0000 32 */ 331 #define SH4A_PCIESTCTLR1 (0x020238) /* R/W R/W 0x0000 0000 32 */ 332 333 #define SH4A_PCIELAR2 (0x020240) /* R/W R/W 0x0000 0000 32 */ 334 #define SH4A_PCIE_020244 (0x020244) /* R/W R/W 0x0000 0000 32 */ 335 #define SH4A_PCIELAMR2 (0x020248) /* R/W R/W 0x0000 0000 32 */ 336 #define SH4A_PCIECSCR2 (0x020250) /* R/W R/W 0x0000 0000 32 */ 337 #define SH4A_PCIECSAR2 (0x020254) /* R/W R/W 0x0000 0000 32 */ 338 #define SH4A_PCIESTCTLR2 (0x020258) /* R/W R/W 0x0000 0000 32 */ 339 340 #define SH4A_PCIELAR3 (0x020260) /* R/W R/W 0x0000 0000 32 */ 341 #define SH4A_PCIE_020264 (0x020264) /* R/W R/W 0x0000 0000 32 */ 342 #define SH4A_PCIELAMR3 (0x020268) /* R/W R/W 0x0000 0000 32 */ 343 #define SH4A_PCIECSCR3 (0x020270) /* R/W R/W 0x0000 0000 32 */ 344 #define SH4A_PCIECSAR3 (0x020274) /* R/W R/W 0x0000 0000 32 */ 345 #define SH4A_PCIESTCTLR3 (0x020278) /* R/W R/W 0x0000 0000 32 */ 346 347 #define SH4A_PCIELAR4 (0x020280) /* R/W R/W 0x0000 0000 32 */ 348 #define SH4A_PCIE_020284 (0x020284) /* R/W R/W 0x0000 0000 32 */ 349 #define SH4A_PCIELAMR4 (0x020288) /* R/W R/W 0x0000 0000 32 */ 350 #define SH4A_PCIECSCR4 (0x020290) /* R/W R/W 0x0000 0000 32 */ 351 #define SH4A_PCIECSAR4 (0x020294) /* R/W R/W 0x0000 0000 32 */ 352 #define SH4A_PCIESTCTLR4 (0x020298) /* R/W R/W 0x0000 0000 32 */ 353 354 #define SH4A_PCIELAR5 (0x0202A0) /* R/W R/W 0x0000 0000 32 */ 355 #define SH4A_PCIE_0202A4 (0x0202A4) /* R/W R/W 0x0000 0000 32 */ 356 #define SH4A_PCIELAMR5 (0x0202A8) /* R/W R/W 0x0000 0000 32 */ 357 #define SH4A_PCIECSCR5 (0x0202B0) /* R/W R/W 0x0000 0000 32 */ 358 #define SH4A_PCIECSAR5 (0x0202B4) /* R/W R/W 0x0000 0000 32 */ 359 #define SH4A_PCIESTCTLR5 (0x0202B8) /* R/W R/W 0x0000 0000 32 */ 360 361 /* PCIEPARL */ 362 #define SH4A_PCIEPARL(x) (0x020400 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */ 363 #define BITS_PAL (18) 364 #define MASK_PAL (0x3fff<<BITS_PAL) 365 366 /* PCIEPARH */ 367 #define SH4A_PCIEPARH(x) (0x020404 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */ 368 #define BITS_PAH (0) 369 #define MASK_PAH (0xffffffff<<BITS_PAH) 370 371 /* PCIEPAMR */ 372 #define SH4A_PCIEPAMR(x) (0x020408 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */ 373 #define BITS_PAM (18) 374 #define MASK_PAM (0x3fff<<BITS_PAM) 375 376 /* PCIEPTCTLR */ 377 #define SH4A_PCIEPTCTLR(x) (0x02040C + ((x) * 0x20)) 378 #define BITS_PARE (31) 379 #define MASK_PARE (0x1<<BITS_PARE) 380 #define BITS_TC (20) 381 #define MASK_TC (0x7<<BITS_TC) 382 #define BITS_T_VC (16) 383 #define MASK_T_VC (0x1<<BITS_T_VC) 384 #define BITS_LOCK (12) 385 #define MASK_LOCK (0x1<<BITS_LOCK) 386 #define BITS_SPC (8) 387 #define MASK_SPC (0x1<<BITS_SPC) 388 389 #define SH4A_PCIEDMAOR (0x021000) /* R/W R/W 0x0000 0000 32 */ 390 #define SH4A_PCIEDMSAR0 (0x021100) /* R/W R/W 0x0000 0000 32 */ 391 #define SH4A_PCIEDMSAHR0 (0x021104) /* R/W R/W 0x0000 0000 32 */ 392 #define SH4A_PCIEDMDAR0 (0x021108) /* R/W R/W 0x0000 0000 32 */ 393 #define SH4A_PCIEDMDAHR0 (0x02110C) /* R/W R/W 0x0000 0000 32 */ 394 #define SH4A_PCIEDMBCNTR0 (0x021110) /* R/W R/W 0x0000 0000 32 */ 395 #define SH4A_PCIEDMSBCNTR0 (0x021114) /* R/W R/W 0x0000 0000 32 */ 396 #define SH4A_PCIEDMSTRR0 (0x021118) /* R/W R/W 0x0000 0000 32 */ 397 #define SH4A_PCIEDMCCAR0 (0x02111C) /* R/W R/W 0x0000 0000 32 */ 398 #define SH4A_PCIEDMCCR0 (0x021120) /* R/W R/W 0x0000 0000 32 */ 399 #define SH4A_PCIEDMCC2R0 (0x021124) /* R/W R/W 0x0000 0000 - */ 400 #define SH4A_PCIEDMCCCR0 (0x021128) /* R/W R/W 0x0000 0000 32 */ 401 #define SH4A_PCIEDMCHSR0 (0x02112C) /* R/W - 0x0000 0000 32 */ 402 #define SH4A_PCIEDMSAR1 (0x021140) /* R/W R/W 0x0000 0000 32 */ 403 #define SH4A_PCIEDMSAHR1 (0x021144) /* R/W R/W 0x0000 0000 32 */ 404 #define SH4A_PCIEDMDAR1 (0x021148) /* R/W R/W 0x0000 0000 32 */ 405 #define SH4A_PCIEDMDAHR1 (0x02114C) /* R/W R/W 0x0000 0000 32 */ 406 #define SH4A_PCIEDMBCNTR1 (0x021150) /* R/W R/W 0x0000 0000 32 */ 407 #define SH4A_PCIEDMSBCNTR1 (0x021154) /* R/W R/W 0x0000 0000 32 */ 408 #define SH4A_PCIEDMSTRR1 (0x021158) /* R/W R/W 0x0000 0000 32 */ 409 #define SH4A_PCIEDMCCAR1 (0x02115C) /* R/W R/W 0x0000 0000 32 */ 410 #define SH4A_PCIEDMCCR1 (0x021160) /* R/W R/W 0x0000 0000 32 */ 411 #define SH4A_PCIEDMCC2R1 (0x021164) /* R/W R/W 0x0000 0000 - */ 412 #define SH4A_PCIEDMCCCR1 (0x021168) /* R/W R/W 0x0000 0000 32 */ 413 #define SH4A_PCIEDMCHSR1 (0x02116C) /* R/W - 0x0000 0000 32 */ 414 #define SH4A_PCIEDMSAR2 (0x021180) /* R/W R/W 0x0000 0000 32 */ 415 #define SH4A_PCIEDMSAHR2 (0x021184) /* R/W R/W 0x0000 0000 32 */ 416 #define SH4A_PCIEDMDAR2 (0x021188) /* R/W R/W 0x0000 0000 32 */ 417 #define SH4A_PCIEDMDAHR2 (0x02118C) /* R/W R/W 0x0000 0000 32 */ 418 #define SH4A_PCIEDMBCNTR2 (0x021190) /* R/W R/W 0x0000 0000 32 */ 419 #define SH4A_PCIEDMSBCNTR2 (0x021194) /* R/W R/W 0x0000 0000 32 */ 420 #define SH4A_PCIEDMSTRR2 (0x021198) /* R/W R/W 0x0000 0000 32 */ 421 #define SH4A_PCIEDMCCAR2 (0x02119C) /* R/W R/W 0x0000 0000 32 */ 422 #define SH4A_PCIEDMCCR2 (0x0211A0) /* R/W R/W 0x0000 0000 32 */ 423 #define SH4A_PCIEDMCC2R2 (0x0211A4) /* R/W R/W 0x0000 0000 - */ 424 #define SH4A_PCIEDMCCCR2 (0x0211A8) /* R/W R/W 0x0000 0000 32 */ 425 #define SH4A_PCIEDMSAR3 (0x0211C0) /* R/W R/W 0x0000 0000 32 */ 426 #define SH4A_PCIEDMSAHR3 (0x0211C4) /* R/W R/W 0x0000 0000 32 */ 427 #define SH4A_PCIEDMDAR3 (0x0211C8) /* R/W R/W 0x0000 0000 32 */ 428 #define SH4A_PCIEDMDAHR3 (0x0211CC) /* R/W R/W 0x0000 0000 32 */ 429 #define SH4A_PCIEDMBCNTR3 (0x0211D0) /* R/W R/W 0x0000 0000 32 */ 430 #define SH4A_PCIEDMSBCNTR3 (0x0211D4) /* R/W R/W 0x0000 0000 32 */ 431 #define SH4A_PCIEDMSTRR3 (0x0211D8) /* R/W R/W 0x0000 0000 32 */ 432 #define SH4A_PCIEDMCCAR3 (0x0211DC) /* R/W R/W 0x0000 0000 32 */ 433 #define SH4A_PCIEDMCCR3 (0x0211E0) /* R/W R/W 0x0000 0000 32 */ 434 #define SH4A_PCIEDMCC2R3 (0x0211E4) /* R/W R/W 0x0000 0000 - */ 435 #define SH4A_PCIEDMCCCR3 (0x0211E8) /* R/W R/W 0x0000 0000 32 */ 436 #define SH4A_PCIEDMCHSR3 (0x0211EC) /* R/W R/W 0x0000 0000 32 */ 437 #define SH4A_PCIEPCICONF0 (0x040000) /* R R - 8/16/32 */ 438 #define SH4A_PCIEPCICONF1 (0x040004) /* R/W R/W 0x0008 0000 8/16/32 */ 439 #define SH4A_PCIEPCICONF2 (0x040008) /* R/W R/W 0xFF00 0000 8/16/32 */ 440 #define SH4A_PCIEPCICONF3 (0x04000C) /* R/W R/W 0x0000 0000 8/16/32 */ 441 #define SH4A_PCIEPCICONF4 (0x040010) /* - R/W - 8/16/32 */ 442 #define SH4A_PCIEPCICONF5 (0x040014) /* - R/W - 8/16/32 */ 443 #define SH4A_PCIEPCICONF6 (0x040018) /* - R/W - 8/16/32 */ 444 #define SH4A_PCIEPCICONF7 (0x04001C) /* - R/W - 8/16/32 */ 445 #define SH4A_PCIEPCICONF8 (0x040020) /* - R/W - 8/16/32 */ 446 #define SH4A_PCIEPCICONF9 (0x040024) /* - R/W - 8/16/32 */ 447 #define SH4A_PCIEPCICONF10 (0x040028) /* R/W R/W 0x0000 0000 8/16/32 */ 448 #define SH4A_PCIEPCICONF11 (0x04002C) /* R/W R/W 0x0000 0000 8/16/32 */ 449 #define SH4A_PCIEPCICONF12 (0x040030) /* R/W R/W 0x0000 0000 8/16/32 */ 450 #define SH4A_PCIEPCICONF13 (0x040034) /* R/W R/W 0x0000 0040 8/16/32 */ 451 #define SH4A_PCIEPCICONF14 (0x040038) /* R/W R/W 0x0000 0000 8/16/32 */ 452 #define SH4A_PCIEPCICONF15 (0x04003C) /* R/W R/W 0x0000 00FF 8/16/32 */ 453 #define SH4A_PCIEPMCAP0 (0x040040) /* R/W R 0x0003 5001 8/16/32 */ 454 #define SH4A_PCIEPMCAP1 (0x040044) /* R/W R/W 0x0000 0000 8/16/32 */ 455 #define SH4A_PCIEMSICAP0 (0x040050) /* R/W R/W 0x0180 7005 8/16/32 */ 456 #define SH4A_PCIEMSICAP1 (0x040054) /* R/W R/W 0x0000 0000 8/16/32 */ 457 #define SH4A_PCIEMSICAP2 (0x040058) /* R/W R/W 0x0000 0000 8/16/32 */ 458 #define SH4A_PCIEMSICAP3 (0x04005C) /* R/W R/W 0x0000 0000 8/16/32 */ 459 #define SH4A_PCIEMSICAP4 (0x040060) /* R/W R/W 0x0000 0000 8/16/32 */ 460 #define SH4A_PCIEMSICAP5 (0x040064) /* R/W R/W 0x0000 0000 8/16/32 */ 461 #define SH4A_PCIEEXPCAP0 (0x040070) /* R/W R/W 0x0001 0010 8/16/32 */ 462 #define SH4A_PCIEEXPCAP1 (0x040074) /* R/W R 0x0000 0005 8/16/32 */ 463 #define SH4A_PCIEEXPCAP2 (0x040078) /* R/W R/W 0x0000 0801 8/16/32 */ 464 #define SH4A_PCIEEXPCAP3 (0x04007C) /* R/W R 0x0003 F421 8/16/32 */ 465 #define SH4A_PCIEEXPCAP4 (0x040080) /* R/W R/W 0x0041 0000 8/16/32 */ 466 #define SH4A_PCIEEXPCAP5 (0x040084) /* R/W R/W 0x0000 0000 8/16/32 */ 467 #define SH4A_PCIEEXPCAP6 (0x040088) /* R/W R/W 0x0000 03C0 8/16/32 */ 468 #define SH4A_PCIEEXPCAP7 (0x04008C) /* R/W R/W 0x0000 0000 8/16/32 */ 469 #define SH4A_PCIEEXPCAP8 (0x040090) /* R/W R/W 0x0000 0000 8/16/32 */ 470 #define SH4A_PCIEVCCAP0 (0x040100) /* R/W R 0x1B01 0002 8/16/32 */ 471 #define SH4A_PCIEVCCAP1 (0x040104) /* R R 0x0000 0001 8/16/32 */ 472 #define SH4A_PCIEVCCAP2 (0x040108) /* R R 0x0000 0000 8/16/32 */ 473 #define SH4A_PCIEVCCAP3 (0x04010C) /* R R/W 0x0000 0000 8/16/32 */ 474 #define SH4A_PCIEVCCAP4 (0x040110) /* R/W R/W 0x0000 0000 8/16/32 */ 475 #define SH4A_PCIEVCCAP5 (0x040114) /* R/W R/W 0x8000 00FF 8/16/32 */ 476 #define SH4A_PCIEVCCAP6 (0x040118) /* R/W R 0x0002 0000 8/16/32 */ 477 #define SH4A_PCIEVCCAP7 (0x04011C) /* R/W R/W 0x0000 0000 8/16/32 */ 478 #define SH4A_PCIEVCCAP8 (0x040120) /* R/W R/W 0x0000 0000 8/16/32 */ 479 #define SH4A_PCIEVCCAP9 (0x040124) /* R/W R 0x0002 0000 8/16/32 */ 480 #define SH4A_PCIENUMCAP0 (0x0001B0) /* RW R 0x0001 0003 8/16/32 */ 481 #define SH4A_PCIENUMCAP1 (0x0001B4) /* R R 0x0000 0000 8/16/32 */ 482 #define SH4A_PCIENUMCAP2 (0x0001B8) /* R R 0x0000 0000 8/16/32 */ 483 #define SH4A_PCIEIDSETR0 (0x041000) /* R/W R 0x0000 FFFF 16/32 */ 484 #define SH4A_PCIEIDSETR1 (0x041004) /* R/W R 0xFF00 0000 16/32 */ 485 #define SH4A_PCIEBAR0SETR (0x041008) /* R/W R 0x0000 0000 16/32 */ 486 #define SH4A_PCIEBAR1SETR (0x04100C) /* R/W R 0x0000 0000 16/32 */ 487 #define SH4A_PCIEBAR2SETR (0x041010) /* R/W R 0x0000 0000 16/32 */ 488 #define SH4A_PCIEBAR3SETR (0x041014) /* R/W R 0x0000 0000 16/32 */ 489 #define SH4A_PCIEBAR4SETR (0x041018) /* R/W R 0x0000 0000 16/32 */ 490 #define SH4A_PCIEBAR5SETR (0x04101C) /* R/W R 0x0000 0000 16/32 */ 491 #define SH4A_PCIECISSETR (0x041020) /* R/W R 0x0000 0000 16/32 */ 492 #define SH4A_PCIEIDSETR2 (0x041024) /* R/W R 0x0000 0000 16/32 */ 493 #define SH4A_PCIEEROMSETR (0x041028) /* R/W R 0x0000 0000 16/32 */ 494 #define SH4A_PCIEDSERSETR0 (0x04102C) /* R/W R 0x0000 0000 16/32 */ 495 #define SH4A_PCIEDSERSETR1 (0x041030) /* R/W R 0x0000 0000 16/32 */ 496 #define SH4A_PCIECTLR (0x041040) /* R/W R 0x0000 0000 16/32 */ 497 #define SH4A_PCIETLSR (0x041044) /* R/W1C R 0x0000 0000 16/32 */ 498 #define SH4A_PCIETLCTLR (0x041048) /* R/W R 0x0000 0000 16/32 */ 499 #define SH4A_PCIEDLSR (0x04104C) /* R/W1C R 0x4003 0000 16/32 */ 500 #define SH4A_PCIEDLCTLR (0x041050) /* R R 0x0000 0000 16/32 */ 501 #define SH4A_PCIEMACSR (0x041054) /* R/W1C R 0x0041 0000 16/32 */ 502 #define SH4A_PCIEMACCTLR (0x041058) /* R/W R 0x0000 0000 16/32 */ 503 #define PCIEMACCTLR_SCR_DIS (1 << 27) /* scramble disable */ 504 #define SH4A_PCIEPMSTR (0x04105C) /* R/W1C R 0x0000 0000 16/32 */ 505 #define SH4A_PCIEPMCTLR (0x041060) /* R/W R 0x0000 0000 16/32 */ 506 #define SH4A_PCIETLINTENR (0x041064) /* R/W R 0x0000 0000 16/32 */ 507 #define SH4A_PCIEDLINTENR (0x041068) /* R/W R 0x0000 0000 16/32 */ 508 #define PCIEDLINTENR_DLL_ACT_ENABLE (1 << 31) /* DL active irq */ 509 #define SH4A_PCIEMACINTENR (0x04106C) /* R/W R 0x0000 0000 16/32 */ 510 #define SH4A_PCIEPMINTENR (0x041070) /* R/W R 0x0000 0000 16/32 */ 511 #define SH4A_PCIETXDCTLR (0x044000) /* R/W - H'00000000_00000000 32/64 */ 512 #define SH4A_PCIETXCTLR (0x044020) /* R/W - H'00000000_00000000 32/64 */ 513 #define SH4A_PCIETXSR (0x044028) /* R - H'00000000_00000000 32/64 */ 514 #define SH4A_PCIETXVC0DCTLR (0x044100) /* R/W - H'00000000_00000000 32/64 */ 515 #define SH4A_PCIETXVC0SR (0x044108) /* R/W - H'00888000_00000000 32/64 */ 516 #define SH4A_PCIEVC0PDTXR (0x044110) /* W - H'00000000_00000000 32/64 */ 517 #define SH4A_PCIEVC0PHTXR (0x044118) /* W - H'00000000_00000000 32/64 */ 518 #define SH4A_PCIEVC0NPDTXR (0x044120) /* W - H'00000000_00000000 32/64 */ 519 #define SH4A_PCIEVC0NPHTXR (0x044128) /* W - H'00000000_00000000 32/64 */ 520 #define SH4A_PCIEVC0CDTXR (0x044130) /* W - H'00000000_00000000 32/64 */ 521 #define SH4A_PCIEVC0CHTXR (0x044138) /* W - H'00000000_00000000 32/64 */ 522 #define SH4A_PCIETXVCXDCTLR (0x044200) /* R/W - H'00000000_00000000 32/64 */ 523 #define SH4A_PCIETXVCXSR (0x044208) /* R/W - H'00000000_00000000 32/64 */ 524 #define SH4A_PCIEVCXPDTXR (0x044210) /* W - H'00000000_00000000 32/64 */ 525 #define SH4A_PCIEVCXPHTXR (0x044218) /* W - H'00000000_00000000 32/64 */ 526 #define SH4A_PCIEVCXNPDTXR (0x044220) /* W - H'00000000_00000000 32/64 */ 527 #define SH4A_PCIEVCXNPHTXR (0x044228) /* W - H'00000000_00000000 32/64 */ 528 #define SH4A_PCIEVCXCDTXR (0x044230) /* W - H'00000000_00000000 32/64 */ 529 #define SH4A_PCIEVCXCHTXR (0x044238) /* W - H'00000000_00000000 32/64 */ 530 #define SH4A_PCIERDCTLR (0x046000) /* RW - H'00000000_00000000 32/64 */ 531 #define SH4A_PCIEERPCTLR (0x046008) /* RW - H'00000000_00000000 32/64 */ 532 #define SH4A_PCIEERPHR (0x046010) /* R - H'00000000_00000000 32/64 */ 533 #define SH4A_PCIEERPERR (0x046018) /* R - H'00000000_00000000 32/64 */ 534 #define SH4A_PCIERXVC0DCTLR (0x046100) /* RW - H'00000000_00000000 32/64 */ 535 #define SH4A_PCIERXVC0SR (0x046108) /* RW - H'00000000_00000000 32/64 */ 536 #define SH4A_PCIEVC0PDRXR (0x046140) /* R - H'00000000_00000000 32/64 */ 537 #define SH4A_PCIEVC0PHRXR (0x046148) /* R - H'00000000_00000000 32/64 */ 538 #define SH4A_PCIEVC0PERR (0x046150) /* R - H'00000000_00000000 32/64 */ 539 #define SH4A_PCIEVC0NPDRXR (0x046158) /* R - H'00000000_00000000 32/64 */ 540 #define SH4A_PCIEVC0NPHRXR (0x046160) /* R - H'00000000_00000000 32/64 */ 541 #define SH4A_PCIEVC0NPERR (0x046168) /* R - H'00000000_00000000 32/64 */ 542 #define SH4A_PCIEVC0CDRXR (0x046170) /* R - H'00000000_00000000 32/64 */ 543 #define SH4A_PCIEVC0CHRXR (0x046178) /* R - H'00000000_00000000 32/64 */ 544 #define SH4A_PCIEVC0CERR (0x046180) /* R - H'00000000_00000000 32/64 */ 545 #define SH4A_PCIERXVCXDCTLR (0x046200) /* RW - H'00000000_00000000 32/64 */ 546 #define SH4A_PCIERXVCXSR (0x046208) /* RW - H'00000000_00000000 32/64 */ 547 #define SH4A_PCIEVCXPDRXR (0x046240) /* R - H'00000000_00000000 32/64 */ 548 #define SH4A_PCIEVCXPHRXR (0x046248) /* R H'00000000_00000000 32/64 */ 549 #define SH4A_PCIEVCXPERR (0x046250) /* R H'00000000_00000000 32/64 */ 550 #define SH4A_PCIEVCXNPDRXR (0x046258) /* R H'00000000_00000000 32/64 */ 551 #define SH4A_PCIEVCXNPHRXR (0x046260) /* R H'00000000_00000000 32/64 */ 552 #define SH4A_PCIEVCXNPERR (0x046268) /* R H'00000000_00000000 32/64 */ 553 #define SH4A_PCIEVCXCDRXR (0x046270) /* R H'00000000_00000000 32/64 */ 554 #define SH4A_PCIEVCXCHRXR (0x046278) /* R H'00000000_00000000 32/64 */ 555 #define SH4A_PCIEVCXCERR (0x046280) /* R H'00000000_00000000 32/64 */ 556 557 /* SSI Register Definition for MSI WORK AROUND --hamada */ 558 #define SH4A_PCI_SSI_BASE 0xFFE00000 /* spw config address */ 559 #define SH4A_PCI_SSI_BASE_LEN 0x00100000 /* 1MB */ 560 561 #define SH4A_SSICR0 (0x000000) 562 #define SH4A_SSICR1 (0x010000) 563 #define SH4A_SSICR2 (0x020000) 564 #define SH4A_SSICR3 (0x030000) 565 566 #define PCI_REG(x) ((x) + 0x40000) 567 568 static inline void 569 pci_write_reg(struct pci_channel *chan, unsigned long val, unsigned long reg) 570 { 571 __raw_writel(val, chan->reg_base + reg); 572 } 573 574 static inline unsigned long 575 pci_read_reg(struct pci_channel *chan, unsigned long reg) 576 { 577 return __raw_readl(chan->reg_base + reg); 578 } 579 580 #endif /* __PCI_SH7786_H */ 581