1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * New-style PCI core. 4 * 5 * Copyright (c) 2004 - 2009 Paul Mundt 6 * Copyright (c) 2002 M. R. Brown 7 * 8 * Modelled after arch/mips/pci/pci.c: 9 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 10 */ 11 #include <linux/kernel.h> 12 #include <linux/mm.h> 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/types.h> 16 #include <linux/dma-debug.h> 17 #include <linux/io.h> 18 #include <linux/mutex.h> 19 #include <linux/spinlock.h> 20 #include <linux/export.h> 21 22 unsigned long PCIBIOS_MIN_IO = 0x0000; 23 unsigned long PCIBIOS_MIN_MEM = 0; 24 25 /* 26 * The PCI controller list. 27 */ 28 static struct pci_channel *hose_head, **hose_tail = &hose_head; 29 30 static int pci_initialized; 31 32 static void pcibios_scanbus(struct pci_channel *hose) 33 { 34 static int next_busno; 35 static int need_domain_info; 36 LIST_HEAD(resources); 37 struct resource *res; 38 resource_size_t offset; 39 int i, ret; 40 struct pci_host_bridge *bridge; 41 42 bridge = pci_alloc_host_bridge(0); 43 if (!bridge) 44 return; 45 46 for (i = 0; i < hose->nr_resources; i++) { 47 res = hose->resources + i; 48 offset = 0; 49 if (res->flags & IORESOURCE_DISABLED) 50 continue; 51 if (res->flags & IORESOURCE_IO) 52 offset = hose->io_offset; 53 else if (res->flags & IORESOURCE_MEM) 54 offset = hose->mem_offset; 55 pci_add_resource_offset(&resources, res, offset); 56 } 57 58 list_splice_init(&resources, &bridge->windows); 59 bridge->dev.parent = NULL; 60 bridge->sysdata = hose; 61 bridge->busnr = next_busno; 62 bridge->ops = hose->pci_ops; 63 bridge->swizzle_irq = pci_common_swizzle; 64 bridge->map_irq = pcibios_map_platform_irq; 65 66 ret = pci_scan_root_bus_bridge(bridge); 67 if (ret) { 68 pci_free_host_bridge(bridge); 69 return; 70 } 71 72 hose->bus = bridge->bus; 73 74 need_domain_info = need_domain_info || hose->index; 75 hose->need_domain_info = need_domain_info; 76 77 next_busno = hose->bus->busn_res.end + 1; 78 /* Don't allow 8-bit bus number overflow inside the hose - 79 reserve some space for bridges. */ 80 if (next_busno > 224) { 81 next_busno = 0; 82 need_domain_info = 1; 83 } 84 85 pci_bus_size_bridges(hose->bus); 86 pci_bus_assign_resources(hose->bus); 87 pci_bus_add_devices(hose->bus); 88 } 89 90 /* 91 * This interrupt-safe spinlock protects all accesses to PCI 92 * configuration space. 93 */ 94 DEFINE_RAW_SPINLOCK(pci_config_lock); 95 static DEFINE_MUTEX(pci_scan_mutex); 96 97 int register_pci_controller(struct pci_channel *hose) 98 { 99 int i; 100 101 for (i = 0; i < hose->nr_resources; i++) { 102 struct resource *res = hose->resources + i; 103 104 if (res->flags & IORESOURCE_DISABLED) 105 continue; 106 107 if (res->flags & IORESOURCE_IO) { 108 if (request_resource(&ioport_resource, res) < 0) 109 goto out; 110 } else { 111 if (request_resource(&iomem_resource, res) < 0) 112 goto out; 113 } 114 } 115 116 *hose_tail = hose; 117 hose_tail = &hose->next; 118 119 /* 120 * Do not panic here but later - this might happen before console init. 121 */ 122 if (!hose->io_map_base) { 123 pr_warn("registering PCI controller with io_map_base unset\n"); 124 } 125 126 /* 127 * Setup the ERR/PERR and SERR timers, if available. 128 */ 129 pcibios_enable_timers(hose); 130 131 /* 132 * Scan the bus if it is register after the PCI subsystem 133 * initialization. 134 */ 135 if (pci_initialized) { 136 mutex_lock(&pci_scan_mutex); 137 pcibios_scanbus(hose); 138 mutex_unlock(&pci_scan_mutex); 139 } 140 141 return 0; 142 143 out: 144 for (--i; i >= 0; i--) 145 release_resource(&hose->resources[i]); 146 147 pr_warn("Skipping PCI bus scan due to resource conflict\n"); 148 return -1; 149 } 150 151 static int __init pcibios_init(void) 152 { 153 struct pci_channel *hose; 154 155 /* Scan all of the recorded PCI controllers. */ 156 for (hose = hose_head; hose; hose = hose->next) 157 pcibios_scanbus(hose); 158 159 pci_initialized = 1; 160 161 return 0; 162 } 163 subsys_initcall(pcibios_init); 164 165 /* 166 * We need to avoid collisions with `mirrored' VGA ports 167 * and other strange ISA hardware, so we always want the 168 * addresses to be allocated in the 0x000-0x0ff region 169 * modulo 0x400. 170 */ 171 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 172 resource_size_t size, resource_size_t align) 173 { 174 struct pci_dev *dev = data; 175 struct pci_channel *hose = dev->sysdata; 176 resource_size_t start = res->start; 177 178 if (res->flags & IORESOURCE_IO) { 179 if (start < PCIBIOS_MIN_IO + hose->resources[0].start) 180 start = PCIBIOS_MIN_IO + hose->resources[0].start; 181 182 /* 183 * Put everything into 0x00-0xff region modulo 0x400. 184 */ 185 if (start & 0x300) 186 start = (start + 0x3ff) & ~0x3ff; 187 } 188 189 return start; 190 } 191 192 static void __init 193 pcibios_bus_report_status_early(struct pci_channel *hose, 194 int top_bus, int current_bus, 195 unsigned int status_mask, int warn) 196 { 197 unsigned int pci_devfn; 198 u16 status; 199 int ret; 200 201 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { 202 if (PCI_FUNC(pci_devfn)) 203 continue; 204 ret = early_read_config_word(hose, top_bus, current_bus, 205 pci_devfn, PCI_STATUS, &status); 206 if (ret != PCIBIOS_SUCCESSFUL) 207 continue; 208 if (status == 0xffff) 209 continue; 210 211 early_write_config_word(hose, top_bus, current_bus, 212 pci_devfn, PCI_STATUS, 213 status & status_mask); 214 if (warn) 215 pr_cont("(%02x:%02x: %04X) ", current_bus, pci_devfn, 216 status); 217 } 218 } 219 220 /* 221 * We can't use pci_find_device() here since we are 222 * called from interrupt context. 223 */ 224 static void __ref 225 pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask, 226 int warn) 227 { 228 struct pci_dev *dev; 229 230 list_for_each_entry(dev, &bus->devices, bus_list) { 231 u16 status; 232 233 /* 234 * ignore host bridge - we handle 235 * that separately 236 */ 237 if (dev->bus->number == 0 && dev->devfn == 0) 238 continue; 239 240 pci_read_config_word(dev, PCI_STATUS, &status); 241 if (status == 0xffff) 242 continue; 243 244 if ((status & status_mask) == 0) 245 continue; 246 247 /* clear the status errors */ 248 pci_write_config_word(dev, PCI_STATUS, status & status_mask); 249 250 if (warn) 251 pr_cont("(%s: %04X) ", pci_name(dev), status); 252 } 253 254 list_for_each_entry(dev, &bus->devices, bus_list) 255 if (dev->subordinate) 256 pcibios_bus_report_status(dev->subordinate, status_mask, warn); 257 } 258 259 void __ref pcibios_report_status(unsigned int status_mask, int warn) 260 { 261 struct pci_channel *hose; 262 263 for (hose = hose_head; hose; hose = hose->next) { 264 if (unlikely(!hose->bus)) 265 pcibios_bus_report_status_early(hose, hose_head->index, 266 hose->index, status_mask, warn); 267 else 268 pcibios_bus_report_status(hose->bus, status_mask, warn); 269 } 270 } 271 272 #ifndef CONFIG_GENERIC_IOMAP 273 274 void __iomem *__pci_ioport_map(struct pci_dev *dev, 275 unsigned long port, unsigned int nr) 276 { 277 struct pci_channel *chan = dev->sysdata; 278 279 if (unlikely(!chan->io_map_base)) { 280 chan->io_map_base = sh_io_port_base; 281 282 if (pci_domains_supported) 283 panic("To avoid data corruption io_map_base MUST be " 284 "set with multiple PCI domains."); 285 } 286 287 return (void __iomem *)(chan->io_map_base + port); 288 } 289 290 void pci_iounmap(struct pci_dev *dev, void __iomem *addr) 291 { 292 iounmap(addr); 293 } 294 EXPORT_SYMBOL(pci_iounmap); 295 296 #endif /* CONFIG_GENERIC_IOMAP */ 297 298 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 299 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 300