1 /* 2 * New-style PCI core. 3 * 4 * Copyright (c) 2004 - 2009 Paul Mundt 5 * Copyright (c) 2002 M. R. Brown 6 * 7 * Modelled after arch/mips/pci/pci.c: 8 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/types.h> 19 #include <linux/dma-debug.h> 20 #include <linux/io.h> 21 #include <linux/mutex.h> 22 #include <linux/spinlock.h> 23 #include <linux/export.h> 24 25 unsigned long PCIBIOS_MIN_IO = 0x0000; 26 unsigned long PCIBIOS_MIN_MEM = 0; 27 28 /* 29 * The PCI controller list. 30 */ 31 static struct pci_channel *hose_head, **hose_tail = &hose_head; 32 33 static int pci_initialized; 34 35 static void __devinit pcibios_scanbus(struct pci_channel *hose) 36 { 37 static int next_busno; 38 static int need_domain_info; 39 LIST_HEAD(resources); 40 struct resource *res; 41 resource_size_t offset; 42 int i; 43 struct pci_bus *bus; 44 45 for (i = 0; i < hose->nr_resources; i++) { 46 res = hose->resources + i; 47 offset = 0; 48 if (res->flags & IORESOURCE_IO) 49 offset = hose->io_offset; 50 else if (res->flags & IORESOURCE_MEM) 51 offset = hose->mem_offset; 52 pci_add_resource_offset(&resources, res, offset); 53 } 54 55 bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose, 56 &resources); 57 hose->bus = bus; 58 59 need_domain_info = need_domain_info || hose->index; 60 hose->need_domain_info = need_domain_info; 61 if (bus) { 62 next_busno = bus->subordinate + 1; 63 /* Don't allow 8-bit bus number overflow inside the hose - 64 reserve some space for bridges. */ 65 if (next_busno > 224) { 66 next_busno = 0; 67 need_domain_info = 1; 68 } 69 70 pci_bus_size_bridges(bus); 71 pci_bus_assign_resources(bus); 72 pci_enable_bridges(bus); 73 } else { 74 pci_free_resource_list(&resources); 75 } 76 } 77 78 /* 79 * This interrupt-safe spinlock protects all accesses to PCI 80 * configuration space. 81 */ 82 DEFINE_RAW_SPINLOCK(pci_config_lock); 83 static DEFINE_MUTEX(pci_scan_mutex); 84 85 int __devinit register_pci_controller(struct pci_channel *hose) 86 { 87 int i; 88 89 for (i = 0; i < hose->nr_resources; i++) { 90 struct resource *res = hose->resources + i; 91 92 if (res->flags & IORESOURCE_IO) { 93 if (request_resource(&ioport_resource, res) < 0) 94 goto out; 95 } else { 96 if (request_resource(&iomem_resource, res) < 0) 97 goto out; 98 } 99 } 100 101 *hose_tail = hose; 102 hose_tail = &hose->next; 103 104 /* 105 * Do not panic here but later - this might happen before console init. 106 */ 107 if (!hose->io_map_base) { 108 printk(KERN_WARNING 109 "registering PCI controller with io_map_base unset\n"); 110 } 111 112 /* 113 * Setup the ERR/PERR and SERR timers, if available. 114 */ 115 pcibios_enable_timers(hose); 116 117 /* 118 * Scan the bus if it is register after the PCI subsystem 119 * initialization. 120 */ 121 if (pci_initialized) { 122 mutex_lock(&pci_scan_mutex); 123 pcibios_scanbus(hose); 124 mutex_unlock(&pci_scan_mutex); 125 } 126 127 return 0; 128 129 out: 130 for (--i; i >= 0; i--) 131 release_resource(&hose->resources[i]); 132 133 printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n"); 134 return -1; 135 } 136 137 static int __init pcibios_init(void) 138 { 139 struct pci_channel *hose; 140 141 /* Scan all of the recorded PCI controllers. */ 142 for (hose = hose_head; hose; hose = hose->next) 143 pcibios_scanbus(hose); 144 145 pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq); 146 147 dma_debug_add_bus(&pci_bus_type); 148 149 pci_initialized = 1; 150 151 return 0; 152 } 153 subsys_initcall(pcibios_init); 154 155 /* 156 * Called after each bus is probed, but before its children 157 * are examined. 158 */ 159 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 160 { 161 } 162 163 /* 164 * We need to avoid collisions with `mirrored' VGA ports 165 * and other strange ISA hardware, so we always want the 166 * addresses to be allocated in the 0x000-0x0ff region 167 * modulo 0x400. 168 */ 169 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 170 resource_size_t size, resource_size_t align) 171 { 172 struct pci_dev *dev = data; 173 struct pci_channel *hose = dev->sysdata; 174 resource_size_t start = res->start; 175 176 if (res->flags & IORESOURCE_IO) { 177 if (start < PCIBIOS_MIN_IO + hose->resources[0].start) 178 start = PCIBIOS_MIN_IO + hose->resources[0].start; 179 180 /* 181 * Put everything into 0x00-0xff region modulo 0x400. 182 */ 183 if (start & 0x300) 184 start = (start + 0x3ff) & ~0x3ff; 185 } 186 187 return start; 188 } 189 190 int pcibios_enable_device(struct pci_dev *dev, int mask) 191 { 192 return pci_enable_resources(dev, mask); 193 } 194 195 void __init pcibios_update_irq(struct pci_dev *dev, int irq) 196 { 197 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 198 } 199 200 char * __devinit __weak pcibios_setup(char *str) 201 { 202 return str; 203 } 204 205 static void __init 206 pcibios_bus_report_status_early(struct pci_channel *hose, 207 int top_bus, int current_bus, 208 unsigned int status_mask, int warn) 209 { 210 unsigned int pci_devfn; 211 u16 status; 212 int ret; 213 214 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { 215 if (PCI_FUNC(pci_devfn)) 216 continue; 217 ret = early_read_config_word(hose, top_bus, current_bus, 218 pci_devfn, PCI_STATUS, &status); 219 if (ret != PCIBIOS_SUCCESSFUL) 220 continue; 221 if (status == 0xffff) 222 continue; 223 224 early_write_config_word(hose, top_bus, current_bus, 225 pci_devfn, PCI_STATUS, 226 status & status_mask); 227 if (warn) 228 printk("(%02x:%02x: %04X) ", current_bus, 229 pci_devfn, status); 230 } 231 } 232 233 /* 234 * We can't use pci_find_device() here since we are 235 * called from interrupt context. 236 */ 237 static void __init_refok 238 pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask, 239 int warn) 240 { 241 struct pci_dev *dev; 242 243 list_for_each_entry(dev, &bus->devices, bus_list) { 244 u16 status; 245 246 /* 247 * ignore host bridge - we handle 248 * that separately 249 */ 250 if (dev->bus->number == 0 && dev->devfn == 0) 251 continue; 252 253 pci_read_config_word(dev, PCI_STATUS, &status); 254 if (status == 0xffff) 255 continue; 256 257 if ((status & status_mask) == 0) 258 continue; 259 260 /* clear the status errors */ 261 pci_write_config_word(dev, PCI_STATUS, status & status_mask); 262 263 if (warn) 264 printk("(%s: %04X) ", pci_name(dev), status); 265 } 266 267 list_for_each_entry(dev, &bus->devices, bus_list) 268 if (dev->subordinate) 269 pcibios_bus_report_status(dev->subordinate, status_mask, warn); 270 } 271 272 void __init_refok pcibios_report_status(unsigned int status_mask, int warn) 273 { 274 struct pci_channel *hose; 275 276 for (hose = hose_head; hose; hose = hose->next) { 277 if (unlikely(!hose->bus)) 278 pcibios_bus_report_status_early(hose, hose_head->index, 279 hose->index, status_mask, warn); 280 else 281 pcibios_bus_report_status(hose->bus, status_mask, warn); 282 } 283 } 284 285 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 286 enum pci_mmap_state mmap_state, int write_combine) 287 { 288 /* 289 * I/O space can be accessed via normal processor loads and stores on 290 * this platform but for now we elect not to do this and portable 291 * drivers should not do this anyway. 292 */ 293 if (mmap_state == pci_mmap_io) 294 return -EINVAL; 295 296 /* 297 * Ignore write-combine; for now only return uncached mappings. 298 */ 299 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 300 301 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 302 vma->vm_end - vma->vm_start, 303 vma->vm_page_prot); 304 } 305 306 #ifndef CONFIG_GENERIC_IOMAP 307 308 void __iomem *__pci_ioport_map(struct pci_dev *dev, 309 unsigned long port, unsigned int nr) 310 { 311 struct pci_channel *chan = dev->sysdata; 312 313 if (unlikely(!chan->io_map_base)) { 314 chan->io_map_base = sh_io_port_base; 315 316 if (pci_domains_supported) 317 panic("To avoid data corruption io_map_base MUST be " 318 "set with multiple PCI domains."); 319 } 320 321 return (void __iomem *)(chan->io_map_base + port); 322 } 323 324 void pci_iounmap(struct pci_dev *dev, void __iomem *addr) 325 { 326 iounmap(addr); 327 } 328 EXPORT_SYMBOL(pci_iounmap); 329 330 #endif /* CONFIG_GENERIC_IOMAP */ 331 332 #ifdef CONFIG_HOTPLUG 333 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 334 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 335 #endif 336