1 /* 2 * New-style PCI core. 3 * 4 * Copyright (c) 2004 - 2009 Paul Mundt 5 * Copyright (c) 2002 M. R. Brown 6 * 7 * Modelled after arch/mips/pci/pci.c: 8 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/types.h> 19 #include <linux/dma-debug.h> 20 #include <linux/io.h> 21 #include <linux/mutex.h> 22 #include <linux/spinlock.h> 23 #include <linux/export.h> 24 25 unsigned long PCIBIOS_MIN_IO = 0x0000; 26 unsigned long PCIBIOS_MIN_MEM = 0; 27 28 /* 29 * The PCI controller list. 30 */ 31 static struct pci_channel *hose_head, **hose_tail = &hose_head; 32 33 static int pci_initialized; 34 35 static void pcibios_scanbus(struct pci_channel *hose) 36 { 37 static int next_busno; 38 static int need_domain_info; 39 LIST_HEAD(resources); 40 struct resource *res; 41 resource_size_t offset; 42 int i, ret; 43 struct pci_host_bridge *bridge; 44 45 bridge = pci_alloc_host_bridge(0); 46 if (!bridge) 47 return; 48 49 for (i = 0; i < hose->nr_resources; i++) { 50 res = hose->resources + i; 51 offset = 0; 52 if (res->flags & IORESOURCE_DISABLED) 53 continue; 54 if (res->flags & IORESOURCE_IO) 55 offset = hose->io_offset; 56 else if (res->flags & IORESOURCE_MEM) 57 offset = hose->mem_offset; 58 pci_add_resource_offset(&resources, res, offset); 59 } 60 61 list_splice_init(&resources, &bridge->windows); 62 bridge->dev.parent = NULL; 63 bridge->sysdata = hose; 64 bridge->busnr = next_busno; 65 bridge->ops = hose->pci_ops; 66 bridge->swizzle_irq = pci_common_swizzle; 67 bridge->map_irq = pcibios_map_platform_irq; 68 69 ret = pci_scan_root_bus_bridge(bridge); 70 if (ret) { 71 pci_free_host_bridge(bridge); 72 return; 73 } 74 75 hose->bus = bridge->bus; 76 77 need_domain_info = need_domain_info || hose->index; 78 hose->need_domain_info = need_domain_info; 79 80 next_busno = hose->bus->busn_res.end + 1; 81 /* Don't allow 8-bit bus number overflow inside the hose - 82 reserve some space for bridges. */ 83 if (next_busno > 224) { 84 next_busno = 0; 85 need_domain_info = 1; 86 } 87 88 pci_bus_size_bridges(hose->bus); 89 pci_bus_assign_resources(hose->bus); 90 pci_bus_add_devices(hose->bus); 91 } 92 93 /* 94 * This interrupt-safe spinlock protects all accesses to PCI 95 * configuration space. 96 */ 97 DEFINE_RAW_SPINLOCK(pci_config_lock); 98 static DEFINE_MUTEX(pci_scan_mutex); 99 100 int register_pci_controller(struct pci_channel *hose) 101 { 102 int i; 103 104 for (i = 0; i < hose->nr_resources; i++) { 105 struct resource *res = hose->resources + i; 106 107 if (res->flags & IORESOURCE_DISABLED) 108 continue; 109 110 if (res->flags & IORESOURCE_IO) { 111 if (request_resource(&ioport_resource, res) < 0) 112 goto out; 113 } else { 114 if (request_resource(&iomem_resource, res) < 0) 115 goto out; 116 } 117 } 118 119 *hose_tail = hose; 120 hose_tail = &hose->next; 121 122 /* 123 * Do not panic here but later - this might happen before console init. 124 */ 125 if (!hose->io_map_base) { 126 printk(KERN_WARNING 127 "registering PCI controller with io_map_base unset\n"); 128 } 129 130 /* 131 * Setup the ERR/PERR and SERR timers, if available. 132 */ 133 pcibios_enable_timers(hose); 134 135 /* 136 * Scan the bus if it is register after the PCI subsystem 137 * initialization. 138 */ 139 if (pci_initialized) { 140 mutex_lock(&pci_scan_mutex); 141 pcibios_scanbus(hose); 142 mutex_unlock(&pci_scan_mutex); 143 } 144 145 return 0; 146 147 out: 148 for (--i; i >= 0; i--) 149 release_resource(&hose->resources[i]); 150 151 printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n"); 152 return -1; 153 } 154 155 static int __init pcibios_init(void) 156 { 157 struct pci_channel *hose; 158 159 /* Scan all of the recorded PCI controllers. */ 160 for (hose = hose_head; hose; hose = hose->next) 161 pcibios_scanbus(hose); 162 163 pci_initialized = 1; 164 165 return 0; 166 } 167 subsys_initcall(pcibios_init); 168 169 /* 170 * We need to avoid collisions with `mirrored' VGA ports 171 * and other strange ISA hardware, so we always want the 172 * addresses to be allocated in the 0x000-0x0ff region 173 * modulo 0x400. 174 */ 175 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 176 resource_size_t size, resource_size_t align) 177 { 178 struct pci_dev *dev = data; 179 struct pci_channel *hose = dev->sysdata; 180 resource_size_t start = res->start; 181 182 if (res->flags & IORESOURCE_IO) { 183 if (start < PCIBIOS_MIN_IO + hose->resources[0].start) 184 start = PCIBIOS_MIN_IO + hose->resources[0].start; 185 186 /* 187 * Put everything into 0x00-0xff region modulo 0x400. 188 */ 189 if (start & 0x300) 190 start = (start + 0x3ff) & ~0x3ff; 191 } 192 193 return start; 194 } 195 196 static void __init 197 pcibios_bus_report_status_early(struct pci_channel *hose, 198 int top_bus, int current_bus, 199 unsigned int status_mask, int warn) 200 { 201 unsigned int pci_devfn; 202 u16 status; 203 int ret; 204 205 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { 206 if (PCI_FUNC(pci_devfn)) 207 continue; 208 ret = early_read_config_word(hose, top_bus, current_bus, 209 pci_devfn, PCI_STATUS, &status); 210 if (ret != PCIBIOS_SUCCESSFUL) 211 continue; 212 if (status == 0xffff) 213 continue; 214 215 early_write_config_word(hose, top_bus, current_bus, 216 pci_devfn, PCI_STATUS, 217 status & status_mask); 218 if (warn) 219 printk("(%02x:%02x: %04X) ", current_bus, 220 pci_devfn, status); 221 } 222 } 223 224 /* 225 * We can't use pci_find_device() here since we are 226 * called from interrupt context. 227 */ 228 static void __ref 229 pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask, 230 int warn) 231 { 232 struct pci_dev *dev; 233 234 list_for_each_entry(dev, &bus->devices, bus_list) { 235 u16 status; 236 237 /* 238 * ignore host bridge - we handle 239 * that separately 240 */ 241 if (dev->bus->number == 0 && dev->devfn == 0) 242 continue; 243 244 pci_read_config_word(dev, PCI_STATUS, &status); 245 if (status == 0xffff) 246 continue; 247 248 if ((status & status_mask) == 0) 249 continue; 250 251 /* clear the status errors */ 252 pci_write_config_word(dev, PCI_STATUS, status & status_mask); 253 254 if (warn) 255 printk("(%s: %04X) ", pci_name(dev), status); 256 } 257 258 list_for_each_entry(dev, &bus->devices, bus_list) 259 if (dev->subordinate) 260 pcibios_bus_report_status(dev->subordinate, status_mask, warn); 261 } 262 263 void __ref pcibios_report_status(unsigned int status_mask, int warn) 264 { 265 struct pci_channel *hose; 266 267 for (hose = hose_head; hose; hose = hose->next) { 268 if (unlikely(!hose->bus)) 269 pcibios_bus_report_status_early(hose, hose_head->index, 270 hose->index, status_mask, warn); 271 else 272 pcibios_bus_report_status(hose->bus, status_mask, warn); 273 } 274 } 275 276 #ifndef CONFIG_GENERIC_IOMAP 277 278 void __iomem *__pci_ioport_map(struct pci_dev *dev, 279 unsigned long port, unsigned int nr) 280 { 281 struct pci_channel *chan = dev->sysdata; 282 283 if (unlikely(!chan->io_map_base)) { 284 chan->io_map_base = sh_io_port_base; 285 286 if (pci_domains_supported) 287 panic("To avoid data corruption io_map_base MUST be " 288 "set with multiple PCI domains."); 289 } 290 291 return (void __iomem *)(chan->io_map_base + port); 292 } 293 294 void pci_iounmap(struct pci_dev *dev, void __iomem *addr) 295 { 296 iounmap(addr); 297 } 298 EXPORT_SYMBOL(pci_iounmap); 299 300 #endif /* CONFIG_GENERIC_IOMAP */ 301 302 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 303 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 304