1 /* 2 * New-style PCI core. 3 * 4 * Copyright (c) 2004 - 2009 Paul Mundt 5 * Copyright (c) 2002 M. R. Brown 6 * 7 * Modelled after arch/mips/pci/pci.c: 8 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org) 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/types.h> 19 #include <linux/dma-debug.h> 20 #include <linux/io.h> 21 #include <linux/mutex.h> 22 23 unsigned long PCIBIOS_MIN_IO = 0x0000; 24 unsigned long PCIBIOS_MIN_MEM = 0; 25 26 /* 27 * The PCI controller list. 28 */ 29 static struct pci_channel *hose_head, **hose_tail = &hose_head; 30 31 static int pci_initialized; 32 33 static void __devinit pcibios_scanbus(struct pci_channel *hose) 34 { 35 static int next_busno; 36 static int need_domain_info; 37 struct pci_bus *bus; 38 39 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 40 hose->bus = bus; 41 42 need_domain_info = need_domain_info || hose->index; 43 hose->need_domain_info = need_domain_info; 44 if (bus) { 45 next_busno = bus->subordinate + 1; 46 /* Don't allow 8-bit bus number overflow inside the hose - 47 reserve some space for bridges. */ 48 if (next_busno > 224) { 49 next_busno = 0; 50 need_domain_info = 1; 51 } 52 53 pci_bus_size_bridges(bus); 54 pci_bus_assign_resources(bus); 55 pci_enable_bridges(bus); 56 } 57 } 58 59 static DEFINE_MUTEX(pci_scan_mutex); 60 61 int __devinit register_pci_controller(struct pci_channel *hose) 62 { 63 int i; 64 65 for (i = 0; i < hose->nr_resources; i++) { 66 struct resource *res = hose->resources + i; 67 68 if (res->flags & IORESOURCE_IO) { 69 if (request_resource(&ioport_resource, res) < 0) 70 goto out; 71 } else { 72 if (request_resource(&iomem_resource, res) < 0) 73 goto out; 74 } 75 } 76 77 *hose_tail = hose; 78 hose_tail = &hose->next; 79 80 /* 81 * Do not panic here but later - this might hapen before console init. 82 */ 83 if (!hose->io_map_base) { 84 printk(KERN_WARNING 85 "registering PCI controller with io_map_base unset\n"); 86 } 87 88 /* 89 * Setup the ERR/PERR and SERR timers, if available. 90 */ 91 pcibios_enable_timers(hose); 92 93 /* 94 * Scan the bus if it is register after the PCI subsystem 95 * initialization. 96 */ 97 if (pci_initialized) { 98 mutex_lock(&pci_scan_mutex); 99 pcibios_scanbus(hose); 100 mutex_unlock(&pci_scan_mutex); 101 } 102 103 return 0; 104 105 out: 106 for (--i; i >= 0; i--) 107 release_resource(&hose->resources[i]); 108 109 printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n"); 110 return -1; 111 } 112 113 static int __init pcibios_init(void) 114 { 115 struct pci_channel *hose; 116 117 /* Scan all of the recorded PCI controllers. */ 118 for (hose = hose_head; hose; hose = hose->next) 119 pcibios_scanbus(hose); 120 121 pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq); 122 123 dma_debug_add_bus(&pci_bus_type); 124 125 pci_initialized = 1; 126 127 return 0; 128 } 129 subsys_initcall(pcibios_init); 130 131 static void pcibios_fixup_device_resources(struct pci_dev *dev, 132 struct pci_bus *bus) 133 { 134 /* Update device resources. */ 135 struct pci_channel *hose = bus->sysdata; 136 unsigned long offset = 0; 137 int i; 138 139 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 140 if (!dev->resource[i].start) 141 continue; 142 if (dev->resource[i].flags & IORESOURCE_PCI_FIXED) 143 continue; 144 if (dev->resource[i].flags & IORESOURCE_IO) 145 offset = hose->io_offset; 146 else if (dev->resource[i].flags & IORESOURCE_MEM) 147 offset = hose->mem_offset; 148 149 dev->resource[i].start += offset; 150 dev->resource[i].end += offset; 151 } 152 } 153 154 /* 155 * Called after each bus is probed, but before its children 156 * are examined. 157 */ 158 void __devinit pcibios_fixup_bus(struct pci_bus *bus) 159 { 160 struct pci_dev *dev = bus->self; 161 struct list_head *ln; 162 struct pci_channel *hose = bus->sysdata; 163 164 if (!dev) { 165 int i; 166 167 for (i = 0; i < hose->nr_resources; i++) 168 bus->resource[i] = hose->resources + i; 169 } 170 171 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 172 dev = pci_dev_b(ln); 173 174 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 175 pcibios_fixup_device_resources(dev, bus); 176 } 177 } 178 179 /* 180 * We need to avoid collisions with `mirrored' VGA ports 181 * and other strange ISA hardware, so we always want the 182 * addresses to be allocated in the 0x000-0x0ff region 183 * modulo 0x400. 184 */ 185 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 186 resource_size_t size, resource_size_t align) 187 { 188 struct pci_dev *dev = data; 189 struct pci_channel *hose = dev->sysdata; 190 resource_size_t start = res->start; 191 192 if (res->flags & IORESOURCE_IO) { 193 if (start < PCIBIOS_MIN_IO + hose->resources[0].start) 194 start = PCIBIOS_MIN_IO + hose->resources[0].start; 195 196 /* 197 * Put everything into 0x00-0xff region modulo 0x400. 198 */ 199 if (start & 0x300) 200 start = (start + 0x3ff) & ~0x3ff; 201 } 202 203 return start; 204 } 205 206 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 207 struct resource *res) 208 { 209 struct pci_channel *hose = dev->sysdata; 210 unsigned long offset = 0; 211 212 if (res->flags & IORESOURCE_IO) 213 offset = hose->io_offset; 214 else if (res->flags & IORESOURCE_MEM) 215 offset = hose->mem_offset; 216 217 region->start = res->start - offset; 218 region->end = res->end - offset; 219 } 220 221 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 222 struct pci_bus_region *region) 223 { 224 struct pci_channel *hose = dev->sysdata; 225 unsigned long offset = 0; 226 227 if (res->flags & IORESOURCE_IO) 228 offset = hose->io_offset; 229 else if (res->flags & IORESOURCE_MEM) 230 offset = hose->mem_offset; 231 232 res->start = region->start + offset; 233 res->end = region->end + offset; 234 } 235 236 int pcibios_enable_device(struct pci_dev *dev, int mask) 237 { 238 u16 cmd, old_cmd; 239 int idx; 240 struct resource *r; 241 242 pci_read_config_word(dev, PCI_COMMAND, &cmd); 243 old_cmd = cmd; 244 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { 245 /* Only set up the requested stuff */ 246 if (!(mask & (1<<idx))) 247 continue; 248 249 r = &dev->resource[idx]; 250 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 251 continue; 252 if ((idx == PCI_ROM_RESOURCE) && 253 (!(r->flags & IORESOURCE_ROM_ENABLE))) 254 continue; 255 if (!r->start && r->end) { 256 printk(KERN_ERR "PCI: Device %s not available " 257 "because of resource collisions\n", 258 pci_name(dev)); 259 return -EINVAL; 260 } 261 if (r->flags & IORESOURCE_IO) 262 cmd |= PCI_COMMAND_IO; 263 if (r->flags & IORESOURCE_MEM) 264 cmd |= PCI_COMMAND_MEMORY; 265 } 266 if (cmd != old_cmd) { 267 printk("PCI: Enabling device %s (%04x -> %04x)\n", 268 pci_name(dev), old_cmd, cmd); 269 pci_write_config_word(dev, PCI_COMMAND, cmd); 270 } 271 return 0; 272 } 273 274 /* 275 * If we set up a device for bus mastering, we need to check and set 276 * the latency timer as it may not be properly set. 277 */ 278 static unsigned int pcibios_max_latency = 255; 279 280 void pcibios_set_master(struct pci_dev *dev) 281 { 282 u8 lat; 283 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 284 if (lat < 16) 285 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 286 else if (lat > pcibios_max_latency) 287 lat = pcibios_max_latency; 288 else 289 return; 290 printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n", 291 pci_name(dev), lat); 292 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 293 } 294 295 void __init pcibios_update_irq(struct pci_dev *dev, int irq) 296 { 297 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 298 } 299 300 char * __devinit pcibios_setup(char *str) 301 { 302 return str; 303 } 304 305 static void __init 306 pcibios_bus_report_status_early(struct pci_channel *hose, 307 int top_bus, int current_bus, 308 unsigned int status_mask, int warn) 309 { 310 unsigned int pci_devfn; 311 u16 status; 312 int ret; 313 314 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { 315 if (PCI_FUNC(pci_devfn)) 316 continue; 317 ret = early_read_config_word(hose, top_bus, current_bus, 318 pci_devfn, PCI_STATUS, &status); 319 if (ret != PCIBIOS_SUCCESSFUL) 320 continue; 321 if (status == 0xffff) 322 continue; 323 324 early_write_config_word(hose, top_bus, current_bus, 325 pci_devfn, PCI_STATUS, 326 status & status_mask); 327 if (warn) 328 printk("(%02x:%02x: %04X) ", current_bus, 329 pci_devfn, status); 330 } 331 } 332 333 /* 334 * We can't use pci_find_device() here since we are 335 * called from interrupt context. 336 */ 337 static void __init_refok 338 pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask, 339 int warn) 340 { 341 struct pci_dev *dev; 342 343 list_for_each_entry(dev, &bus->devices, bus_list) { 344 u16 status; 345 346 /* 347 * ignore host bridge - we handle 348 * that separately 349 */ 350 if (dev->bus->number == 0 && dev->devfn == 0) 351 continue; 352 353 pci_read_config_word(dev, PCI_STATUS, &status); 354 if (status == 0xffff) 355 continue; 356 357 if ((status & status_mask) == 0) 358 continue; 359 360 /* clear the status errors */ 361 pci_write_config_word(dev, PCI_STATUS, status & status_mask); 362 363 if (warn) 364 printk("(%s: %04X) ", pci_name(dev), status); 365 } 366 367 list_for_each_entry(dev, &bus->devices, bus_list) 368 if (dev->subordinate) 369 pcibios_bus_report_status(dev->subordinate, status_mask, warn); 370 } 371 372 void __init_refok pcibios_report_status(unsigned int status_mask, int warn) 373 { 374 struct pci_channel *hose; 375 376 for (hose = hose_head; hose; hose = hose->next) { 377 if (unlikely(!hose->bus)) 378 pcibios_bus_report_status_early(hose, hose_head->index, 379 hose->index, status_mask, warn); 380 else 381 pcibios_bus_report_status(hose->bus, status_mask, warn); 382 } 383 } 384 385 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 386 enum pci_mmap_state mmap_state, int write_combine) 387 { 388 /* 389 * I/O space can be accessed via normal processor loads and stores on 390 * this platform but for now we elect not to do this and portable 391 * drivers should not do this anyway. 392 */ 393 if (mmap_state == pci_mmap_io) 394 return -EINVAL; 395 396 /* 397 * Ignore write-combine; for now only return uncached mappings. 398 */ 399 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 400 401 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 402 vma->vm_end - vma->vm_start, 403 vma->vm_page_prot); 404 } 405 406 #ifndef CONFIG_GENERIC_IOMAP 407 408 static void __iomem *ioport_map_pci(struct pci_dev *dev, 409 unsigned long port, unsigned int nr) 410 { 411 struct pci_channel *chan = dev->sysdata; 412 413 if (unlikely(!chan->io_map_base)) { 414 chan->io_map_base = generic_io_base; 415 416 if (pci_domains_supported) 417 panic("To avoid data corruption io_map_base MUST be " 418 "set with multiple PCI domains."); 419 } 420 421 422 return (void __iomem *)(chan->io_map_base + port); 423 } 424 425 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 426 { 427 resource_size_t start = pci_resource_start(dev, bar); 428 resource_size_t len = pci_resource_len(dev, bar); 429 unsigned long flags = pci_resource_flags(dev, bar); 430 431 if (unlikely(!len || !start)) 432 return NULL; 433 if (maxlen && len > maxlen) 434 len = maxlen; 435 436 if (flags & IORESOURCE_IO) 437 return ioport_map_pci(dev, start, len); 438 if (flags & IORESOURCE_MEM) { 439 if (flags & IORESOURCE_CACHEABLE) 440 return ioremap(start, len); 441 return ioremap_nocache(start, len); 442 } 443 444 return NULL; 445 } 446 EXPORT_SYMBOL(pci_iomap); 447 448 void pci_iounmap(struct pci_dev *dev, void __iomem *addr) 449 { 450 iounmap(addr); 451 } 452 EXPORT_SYMBOL(pci_iounmap); 453 454 #endif /* CONFIG_GENERIC_IOMAP */ 455 456 #ifdef CONFIG_HOTPLUG 457 EXPORT_SYMBOL(pcibios_resource_to_bus); 458 EXPORT_SYMBOL(pcibios_bus_to_resource); 459 EXPORT_SYMBOL(PCIBIOS_MIN_IO); 460 EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 461 #endif 462