1 /* 2 * Low-Level PCI Support for the SH7780 3 * 4 * Dustin McIntire (dustin@sensoria.com) 5 * Derived from arch/i386/kernel/pci-*.c which bore the message: 6 * (c) 1999--2000 Martin Mares <mj@ucw.cz> 7 * 8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org> 9 * With cleanup by Paul van Gool <pvangool@mimotech.com> 10 * 11 * May be copied or modified under the terms of the GNU General Public 12 * License. See linux/COPYING for more information. 13 * 14 */ 15 #undef DEBUG 16 17 #include <linux/types.h> 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/pci.h> 21 #include <linux/errno.h> 22 #include <linux/delay.h> 23 #include "pci-sh4.h" 24 25 /* 26 * Initialization. Try all known PCI access methods. Note that we support 27 * using both PCI BIOS and direct access: in such cases, we use I/O ports 28 * to access config space. 29 * 30 * Note that the platform specific initialization (BSC registers, and memory 31 * space mapping) will be called via the platform defined function 32 * pcibios_init_platform(). 33 */ 34 int __init sh7780_pci_init(struct pci_channel *chan) 35 { 36 unsigned int id; 37 int ret, match = 0; 38 39 pr_debug("PCI: Starting intialization.\n"); 40 41 chan->reg_base = 0xfe040000; 42 chan->io_base = 0xfe200000; 43 44 ctrl_outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */ 45 46 /* check for SH7780/SH7780R hardware */ 47 id = pci_read_reg(chan, SH7780_PCIVID); 48 if ((id & 0xffff) == SH7780_VENDOR_ID) { 49 switch ((id >> 16) & 0xffff) { 50 case SH7763_DEVICE_ID: 51 case SH7780_DEVICE_ID: 52 case SH7781_DEVICE_ID: 53 case SH7785_DEVICE_ID: 54 match = 1; 55 break; 56 } 57 } 58 59 if (unlikely(!match)) { 60 printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id); 61 return -ENODEV; 62 } 63 64 if ((ret = sh4_pci_check_direct(chan)) != 0) 65 return ret; 66 67 return pcibios_init_platform(); 68 } 69 70 int __init sh7780_pcic_init(struct pci_channel *chan, 71 struct sh4_pci_address_map *map) 72 { 73 u32 word; 74 75 /* set the command/status bits to: 76 * Wait Cycle Control + Parity Enable + Bus Master + 77 * Mem space enable 78 */ 79 pci_write_reg(chan, 0x00000046, SH7780_PCICMD); 80 81 /* define this host as the host bridge */ 82 word = PCI_BASE_CLASS_BRIDGE << 24; 83 pci_write_reg(chan, word, SH7780_PCIRID); 84 85 /* Set IO and Mem windows to local address 86 * Make PCI and local address the same for easy 1 to 1 mapping 87 */ 88 pci_write_reg(chan, map->window0.size - 0xfffff, SH4_PCILSR0); 89 pci_write_reg(chan, map->window1.size - 0xfffff, SH4_PCILSR1); 90 /* Set the values on window 0 PCI config registers */ 91 pci_write_reg(chan, map->window0.base, SH4_PCILAR0); 92 pci_write_reg(chan, map->window0.base, SH7780_PCIMBAR0); 93 /* Set the values on window 1 PCI config registers */ 94 pci_write_reg(chan, map->window1.base, SH4_PCILAR1); 95 pci_write_reg(chan, map->window1.base, SH7780_PCIMBAR1); 96 97 /* Apply any last-minute PCIC fixups */ 98 pci_fixup_pcic(chan); 99 100 /* SH7780 init done, set central function init complete */ 101 /* use round robin mode to stop a device starving/overruning */ 102 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO; 103 pci_write_reg(chan, word, SH4_PCICR); 104 105 return 0; 106 } 107