1 /* 2 * Low-Level PCI Support for the SH7751 3 * 4 * Dustin McIntire (dustin@sensoria.com) 5 * Derived from arch/i386/kernel/pci-*.c which bore the message: 6 * (c) 1999--2000 Martin Mares <mj@ucw.cz> 7 * 8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org> 9 * With cleanup by Paul van Gool <pvangool@mimotech.com> 10 * 11 * May be copied or modified under the terms of the GNU General Public 12 * License. See linux/COPYING for more information. 13 * 14 */ 15 #undef DEBUG 16 17 #include <linux/init.h> 18 #include <linux/pci.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/delay.h> 22 #include "pci-sh4.h" 23 #include <asm/addrspace.h> 24 #include <asm/io.h> 25 26 /* 27 * Initialization. Try all known PCI access methods. Note that we support 28 * using both PCI BIOS and direct access: in such cases, we use I/O ports 29 * to access config space. 30 * 31 * Note that the platform specific initialization (BSC registers, and memory 32 * space mapping) will be called via the platform defined function 33 * pcibios_init_platform(). 34 */ 35 int __init sh7751_pci_init(struct pci_channel *chan) 36 { 37 unsigned int id; 38 int ret; 39 40 pr_debug("PCI: Starting intialization.\n"); 41 42 chan->reg_base = 0xfe200000; 43 chan->io_base = 0xfe240000; 44 45 /* check for SH7751/SH7751R hardware */ 46 id = pci_read_reg(chan, SH7751_PCICONF0); 47 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) && 48 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) { 49 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id); 50 return -ENODEV; 51 } 52 53 if ((ret = sh4_pci_check_direct(chan)) != 0) 54 return ret; 55 56 return pcibios_init_platform(); 57 } 58 59 static int __init __area_sdram_check(struct pci_channel *chan, 60 unsigned int area) 61 { 62 u32 word; 63 64 word = ctrl_inl(SH7751_BCR1); 65 /* check BCR for SDRAM in area */ 66 if (((word >> area) & 1) == 0) { 67 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n", 68 area, word); 69 return 0; 70 } 71 pci_write_reg(chan, word, SH4_PCIBCR1); 72 73 word = (u16)ctrl_inw(SH7751_BCR2); 74 /* check BCR2 for 32bit SDRAM interface*/ 75 if (((word >> (area << 1)) & 0x3) != 0x3) { 76 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n", 77 area, word); 78 return 0; 79 } 80 pci_write_reg(chan, word, SH4_PCIBCR2); 81 82 return 1; 83 } 84 85 int __init sh7751_pcic_init(struct pci_channel *chan, 86 struct sh4_pci_address_map *map) 87 { 88 u32 reg; 89 u32 word; 90 91 /* Set the BCR's to enable PCI access */ 92 reg = ctrl_inl(SH7751_BCR1); 93 reg |= 0x80000; 94 ctrl_outl(reg, SH7751_BCR1); 95 96 /* Turn the clocks back on (not done in reset)*/ 97 pci_write_reg(chan, 0, SH4_PCICLKR); 98 /* Clear Powerdown IRQ's (not done in reset) */ 99 word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0; 100 pci_write_reg(chan, word, SH4_PCIPINT); 101 102 /* set the command/status bits to: 103 * Wait Cycle Control + Parity Enable + Bus Master + 104 * Mem space enable 105 */ 106 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER | 107 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES; 108 pci_write_reg(chan, word, SH7751_PCICONF1); 109 110 /* define this host as the host bridge */ 111 word = PCI_BASE_CLASS_BRIDGE << 24; 112 pci_write_reg(chan, word, SH7751_PCICONF2); 113 114 /* Set IO and Mem windows to local address 115 * Make PCI and local address the same for easy 1 to 1 mapping 116 * Window0 = map->window0.size @ non-cached area base = SDRAM 117 * Window1 = map->window1.size @ cached area base = SDRAM 118 */ 119 word = map->window0.size - 1; 120 pci_write_reg(chan, word, SH4_PCILSR0); 121 word = map->window1.size - 1; 122 pci_write_reg(chan, word, SH4_PCILSR1); 123 /* Set the values on window 0 PCI config registers */ 124 word = P2SEGADDR(map->window0.base); 125 pci_write_reg(chan, word, SH4_PCILAR0); 126 pci_write_reg(chan, word, SH7751_PCICONF5); 127 /* Set the values on window 1 PCI config registers */ 128 word = PHYSADDR(map->window1.base); 129 pci_write_reg(chan, word, SH4_PCILAR1); 130 pci_write_reg(chan, word, SH7751_PCICONF6); 131 132 /* Set the local 16MB PCI memory space window to 133 * the lowest PCI mapped address 134 */ 135 word = chan->mem_resource->start & SH4_PCIMBR_MASK; 136 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word); 137 pci_write_reg(chan, word , SH4_PCIMBR); 138 139 /* Map IO space into PCI IO window: 140 * IO addresses will be translated to the PCI IO window base address 141 */ 142 pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%lx\n", 143 chan->io_resource->start, chan->io_resource->end, 144 chan->io_base + chan->io_resource->start); 145 146 /* Make sure the MSB's of IO window are set to access PCI space 147 * correctly */ 148 word = chan->io_resource->start & SH4_PCIIOBR_MASK; 149 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word); 150 pci_write_reg(chan, word, SH4_PCIIOBR); 151 152 /* Set PCI WCRx, BCRx's, copy from BSC locations */ 153 154 /* check BCR for SDRAM in specified area */ 155 switch (map->window0.base) { 156 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break; 157 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break; 158 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break; 159 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(chan, 3); break; 160 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(chan, 4); break; 161 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(chan, 5); break; 162 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(chan, 6); break; 163 } 164 165 if (!word) 166 return -1; 167 168 /* configure the wait control registers */ 169 word = ctrl_inl(SH7751_WCR1); 170 pci_write_reg(chan, word, SH4_PCIWCR1); 171 word = ctrl_inl(SH7751_WCR2); 172 pci_write_reg(chan, word, SH4_PCIWCR2); 173 word = ctrl_inl(SH7751_WCR3); 174 pci_write_reg(chan, word, SH4_PCIWCR3); 175 word = ctrl_inl(SH7751_MCR); 176 pci_write_reg(chan, word, SH4_PCIMCR); 177 178 /* NOTE: I'm ignoring the PCI error IRQs for now.. 179 * TODO: add support for the internal error interrupts and 180 * DMA interrupts... 181 */ 182 183 pci_fixup_pcic(chan); 184 185 /* SH7751 init done, set central function init complete */ 186 /* use round robin mode to stop a device starving/overruning */ 187 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM; 188 pci_write_reg(chan, word, SH4_PCICR); 189 190 return 0; 191 } 192