1 /* 2 * Generic SH7786 PCI-Express operations. 3 * 4 * Copyright (C) 2009 - 2010 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License v2. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/pci.h> 13 #include <linux/io.h> 14 #include <linux/spinlock.h> 15 #include "pcie-sh7786.h" 16 17 enum { 18 PCI_ACCESS_READ, 19 PCI_ACCESS_WRITE, 20 }; 21 22 static DEFINE_SPINLOCK(sh7786_pcie_lock); 23 24 static int sh7786_pcie_config_access(unsigned char access_type, 25 struct pci_bus *bus, unsigned int devfn, int where, u32 *data) 26 { 27 struct pci_channel *chan = bus->sysdata; 28 int dev, func, type, reg; 29 30 dev = PCI_SLOT(devfn); 31 func = PCI_FUNC(devfn); 32 type = !!bus->parent; 33 reg = where & ~3; 34 35 if (bus->number > 255 || dev > 31 || func > 7) 36 return PCIBIOS_FUNC_NOT_SUPPORTED; 37 38 /* 39 * While each channel has its own memory-mapped extended config 40 * space, it's generally only accessible when in endpoint mode. 41 * When in root complex mode, the controller is unable to target 42 * itself with either type 0 or type 1 accesses, and indeed, any 43 * controller initiated target transfer to its own config space 44 * result in a completer abort. 45 * 46 * Each channel effectively only supports a single device, but as 47 * the same channel <-> device access works for any PCI_SLOT() 48 * value, we cheat a bit here and bind the controller's config 49 * space to devfn 0 in order to enable self-enumeration. In this 50 * case the regular PAR/PDR path is sidelined and the mangled 51 * config access itself is initiated as a SuperHyway transaction. 52 */ 53 if (pci_is_root_bus(bus)) { 54 if (dev == 0) { 55 if (access_type == PCI_ACCESS_READ) 56 *data = pci_read_reg(chan, PCI_REG(reg)); 57 else 58 pci_write_reg(chan, *data, PCI_REG(reg)); 59 60 return PCIBIOS_SUCCESSFUL; 61 } else if (dev > 1) 62 return PCIBIOS_DEVICE_NOT_FOUND; 63 } 64 65 /* Clear errors */ 66 pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR); 67 68 /* Set the PIO address */ 69 pci_write_reg(chan, (bus->number << 24) | (dev << 19) | 70 (func << 16) | reg, SH4A_PCIEPAR); 71 72 /* Enable the configuration access */ 73 pci_write_reg(chan, (1 << 31) | (type << 8), SH4A_PCIEPCTLR); 74 75 /* Check for errors */ 76 if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10) 77 return PCIBIOS_DEVICE_NOT_FOUND; 78 79 /* Check for master and target aborts */ 80 if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28))) 81 return PCIBIOS_DEVICE_NOT_FOUND; 82 83 if (access_type == PCI_ACCESS_READ) 84 *data = pci_read_reg(chan, SH4A_PCIEPDR); 85 else 86 pci_write_reg(chan, *data, SH4A_PCIEPDR); 87 88 /* Disable the configuration access */ 89 pci_write_reg(chan, 0, SH4A_PCIEPCTLR); 90 91 return PCIBIOS_SUCCESSFUL; 92 } 93 94 static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn, 95 int where, int size, u32 *val) 96 { 97 unsigned long flags; 98 int ret; 99 u32 data; 100 101 if ((size == 2) && (where & 1)) 102 return PCIBIOS_BAD_REGISTER_NUMBER; 103 else if ((size == 4) && (where & 3)) 104 return PCIBIOS_BAD_REGISTER_NUMBER; 105 106 spin_lock_irqsave(&sh7786_pcie_lock, flags); 107 ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus, 108 devfn, where, &data); 109 if (ret != PCIBIOS_SUCCESSFUL) { 110 *val = 0xffffffff; 111 goto out; 112 } 113 114 if (size == 1) 115 *val = (data >> ((where & 3) << 3)) & 0xff; 116 else if (size == 2) 117 *val = (data >> ((where & 2) << 3)) & 0xffff; 118 else 119 *val = data; 120 121 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x " 122 "where=0x%04x size=%d val=0x%08lx\n", bus->number, 123 devfn, where, size, (unsigned long)*val); 124 125 out: 126 spin_unlock_irqrestore(&sh7786_pcie_lock, flags); 127 return ret; 128 } 129 130 static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn, 131 int where, int size, u32 val) 132 { 133 unsigned long flags; 134 int shift, ret; 135 u32 data; 136 137 if ((size == 2) && (where & 1)) 138 return PCIBIOS_BAD_REGISTER_NUMBER; 139 else if ((size == 4) && (where & 3)) 140 return PCIBIOS_BAD_REGISTER_NUMBER; 141 142 spin_lock_irqsave(&sh7786_pcie_lock, flags); 143 ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus, 144 devfn, where, &data); 145 if (ret != PCIBIOS_SUCCESSFUL) 146 goto out; 147 148 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x " 149 "where=0x%04x size=%d val=%08lx\n", bus->number, 150 devfn, where, size, (unsigned long)val); 151 152 if (size == 1) { 153 shift = (where & 3) << 3; 154 data &= ~(0xff << shift); 155 data |= ((val & 0xff) << shift); 156 } else if (size == 2) { 157 shift = (where & 2) << 3; 158 data &= ~(0xffff << shift); 159 data |= ((val & 0xffff) << shift); 160 } else 161 data = val; 162 163 ret = sh7786_pcie_config_access(PCI_ACCESS_WRITE, bus, 164 devfn, where, &data); 165 out: 166 spin_unlock_irqrestore(&sh7786_pcie_lock, flags); 167 return ret; 168 } 169 170 struct pci_ops sh7786_pci_ops = { 171 .read = sh7786_pcie_read, 172 .write = sh7786_pcie_write, 173 }; 174