12d5efc19SPaul Mundt #include <linux/kernel.h> 22d5efc19SPaul Mundt #include <linux/types.h> 32d5efc19SPaul Mundt #include <linux/init.h> 42d5efc19SPaul Mundt #include <linux/delay.h> 52d5efc19SPaul Mundt #include <linux/pci.h> 62d5efc19SPaul Mundt #include <linux/io.h> 72d5efc19SPaul Mundt #include "pci-sh4.h" 82d5efc19SPaul Mundt 9d5341942SRalf Baechle int __init pcibios_map_platform_irq(const struct pci_dev *, u8 slot, u8 pin) 102d5efc19SPaul Mundt { 112d5efc19SPaul Mundt switch (slot) { 122d5efc19SPaul Mundt case 0: return 13; 132d5efc19SPaul Mundt case 1: return 13; /* AMD Ethernet controller */ 142d5efc19SPaul Mundt case 2: return -1; 152d5efc19SPaul Mundt case 3: return -1; 162d5efc19SPaul Mundt case 4: return -1; 172d5efc19SPaul Mundt default: 182d5efc19SPaul Mundt printk("PCI: Bad IRQ mapping request for slot %d\n", slot); 192d5efc19SPaul Mundt return -1; 202d5efc19SPaul Mundt } 212d5efc19SPaul Mundt } 222d5efc19SPaul Mundt 232d5efc19SPaul Mundt #define PCIMCR_MRSET_OFF 0xBFFFFFFF 242d5efc19SPaul Mundt #define PCIMCR_RFSH_OFF 0xFFFFFFFB 252d5efc19SPaul Mundt 262d5efc19SPaul Mundt /* 272d5efc19SPaul Mundt * Only long word accesses of the PCIC's internal local registers and the 282d5efc19SPaul Mundt * configuration registers from the CPU is supported. 292d5efc19SPaul Mundt */ 302d5efc19SPaul Mundt #define PCIC_WRITE(x,v) writel((v), PCI_REG(x)) 312d5efc19SPaul Mundt #define PCIC_READ(x) readl(PCI_REG(x)) 322d5efc19SPaul Mundt 332d5efc19SPaul Mundt /* 342d5efc19SPaul Mundt * Description: This function sets up and initializes the pcic, sets 352d5efc19SPaul Mundt * up the BARS, maps the DRAM into the address space etc, etc. 362d5efc19SPaul Mundt */ 372d5efc19SPaul Mundt int pci_fixup_pcic(struct pci_channel *chan) 382d5efc19SPaul Mundt { 392d5efc19SPaul Mundt unsigned long bcr1, wcr1, wcr2, wcr3, mcr; 402d5efc19SPaul Mundt unsigned short bcr2; 412d5efc19SPaul Mundt 422d5efc19SPaul Mundt /* 432d5efc19SPaul Mundt * Initialize the slave bus controller on the pcic. The values used 442d5efc19SPaul Mundt * here should not be hardcoded, but they should be taken from the bsc 452d5efc19SPaul Mundt * on the processor, to make this function as generic as possible. 462d5efc19SPaul Mundt * (i.e. Another sbc may usr different SDRAM timing settings -- in order 472d5efc19SPaul Mundt * for the pcic to work, its settings need to be exactly the same.) 482d5efc19SPaul Mundt */ 492d5efc19SPaul Mundt bcr1 = (*(volatile unsigned long*)(SH7751_BCR1)); 502d5efc19SPaul Mundt bcr2 = (*(volatile unsigned short*)(SH7751_BCR2)); 512d5efc19SPaul Mundt wcr1 = (*(volatile unsigned long*)(SH7751_WCR1)); 522d5efc19SPaul Mundt wcr2 = (*(volatile unsigned long*)(SH7751_WCR2)); 532d5efc19SPaul Mundt wcr3 = (*(volatile unsigned long*)(SH7751_WCR3)); 542d5efc19SPaul Mundt mcr = (*(volatile unsigned long*)(SH7751_MCR)); 552d5efc19SPaul Mundt 562d5efc19SPaul Mundt bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */ 572d5efc19SPaul Mundt (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1; 582d5efc19SPaul Mundt 592d5efc19SPaul Mundt bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ 602d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */ 612d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */ 622d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */ 632d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */ 642d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */ 652d5efc19SPaul Mundt mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; 662d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */ 672d5efc19SPaul Mundt 682d5efc19SPaul Mundt 692d5efc19SPaul Mundt /* Enable all interrupts, so we know what to fix */ 702d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff); 712d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f); 722d5efc19SPaul Mundt 732d5efc19SPaul Mundt /* Set up standard PCI config registers */ 742d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */ 752d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */ 762d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */ 772d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */ 782d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */ 792d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */ 802d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */ 812d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */ 822d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */ 832d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */ 842d5efc19SPaul Mundt 852d5efc19SPaul Mundt /* Now turn it on... */ 862d5efc19SPaul Mundt PCIC_WRITE(SH7751_PCICR, 0xa5000001); 872d5efc19SPaul Mundt 882d5efc19SPaul Mundt /* 892d5efc19SPaul Mundt * Set PCIMBR and PCIIOBR here, assuming a single window 902d5efc19SPaul Mundt * (16M MEM, 256K IO) is enough. If a larger space is 912d5efc19SPaul Mundt * needed, the readx/writex and inx/outx functions will 922d5efc19SPaul Mundt * have to do more (e.g. setting registers for each call). 932d5efc19SPaul Mundt */ 942d5efc19SPaul Mundt 952d5efc19SPaul Mundt /* 962d5efc19SPaul Mundt * Set the MBR so PCI address is one-to-one with window, 972d5efc19SPaul Mundt * meaning all calls go straight through... use BUG_ON to 982d5efc19SPaul Mundt * catch erroneous assumption. 992d5efc19SPaul Mundt */ 100b6c58b1dSPaul Mundt BUG_ON(chan->resources[1].start != SH7751_PCI_MEMORY_BASE); 1012d5efc19SPaul Mundt 102b6c58b1dSPaul Mundt PCIC_WRITE(SH7751_PCIMBR, chan->resources[1].start); 1032d5efc19SPaul Mundt 1042d5efc19SPaul Mundt /* Set IOBR for window containing area specified in pci.h */ 105b6c58b1dSPaul Mundt PCIC_WRITE(SH7751_PCIIOBR, (chan->resources[0].start & SH7751_PCIIOBR_MASK)); 1062d5efc19SPaul Mundt 1072d5efc19SPaul Mundt /* All done, may as well say so... */ 1082d5efc19SPaul Mundt printk("SH7751 PCI: Finished initialization of the PCI controller\n"); 1092d5efc19SPaul Mundt 1102d5efc19SPaul Mundt return 1; 1112d5efc19SPaul Mundt } 112