11da177e4SLinus Torvalds /*
21da177e4SLinus Torvalds  * arch/sh/drivers/pci/fixups-rts7751r2d.c
31da177e4SLinus Torvalds  *
437c8ac36SPaul Mundt  * RTS7751R2D / LBOXRE2 PCI fixups
51da177e4SLinus Torvalds  *
61da177e4SLinus Torvalds  * Copyright (C) 2003  Lineo uSolutions, Inc.
71da177e4SLinus Torvalds  * Copyright (C) 2004  Paul Mundt
837c8ac36SPaul Mundt  * Copyright (C) 2007  Nobuhiro Iwamatsu
91da177e4SLinus Torvalds  *
101da177e4SLinus Torvalds  * This file is subject to the terms and conditions of the GNU General Public
111da177e4SLinus Torvalds  * License.  See the file "COPYING" in the main directory of this archive
121da177e4SLinus Torvalds  * for more details.
131da177e4SLinus Torvalds  */
14b8b47bfbSMagnus Damm #include <linux/pci.h>
1537c8ac36SPaul Mundt #include <mach/lboxre2.h>
1637c8ac36SPaul Mundt #include <mach/r2d.h>
17959f85f8SPaul Mundt #include "pci-sh4.h"
1837c8ac36SPaul Mundt #include <asm/machtypes.h>
191da177e4SLinus Torvalds 
201da177e4SLinus Torvalds #define PCIMCR_MRSET_OFF	0xBFFFFFFF
211da177e4SLinus Torvalds #define PCIMCR_RFSH_OFF		0xFFFFFFFB
221da177e4SLinus Torvalds 
2337c8ac36SPaul Mundt static u8 rts7751r2d_irq_tab[] __initdata = {
2437c8ac36SPaul Mundt 	IRQ_PCI_INTA,
2537c8ac36SPaul Mundt 	IRQ_PCI_INTB,
2637c8ac36SPaul Mundt 	IRQ_PCI_INTC,
2737c8ac36SPaul Mundt 	IRQ_PCI_INTD,
2837c8ac36SPaul Mundt };
2937c8ac36SPaul Mundt 
3037c8ac36SPaul Mundt static char lboxre2_irq_tab[] __initdata = {
3137c8ac36SPaul Mundt 	IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
3237c8ac36SPaul Mundt };
3337c8ac36SPaul Mundt 
3437c8ac36SPaul Mundt int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
3537c8ac36SPaul Mundt {
3637c8ac36SPaul Mundt 	if (mach_is_lboxre2())
3737c8ac36SPaul Mundt 		return lboxre2_irq_tab[slot];
3837c8ac36SPaul Mundt 	else
3937c8ac36SPaul Mundt 		return rts7751r2d_irq_tab[slot];
4037c8ac36SPaul Mundt }
4137c8ac36SPaul Mundt 
42b8b47bfbSMagnus Damm int pci_fixup_pcic(struct pci_channel *chan)
431da177e4SLinus Torvalds {
441da177e4SLinus Torvalds 	unsigned long bcr1, mcr;
451da177e4SLinus Torvalds 
46e036eaa6SMagnus Damm 	bcr1 = ctrl_inl(SH7751_BCR1);
471da177e4SLinus Torvalds 	bcr1 |= 0x40080000;	/* Enable Bit 19 BREQEN, set PCIC to slave */
48b8b47bfbSMagnus Damm 	pci_write_reg(chan, bcr1, SH4_PCIBCR1);
491da177e4SLinus Torvalds 
501da177e4SLinus Torvalds 	/* Enable all interrupts, so we known what to fix */
51b8b47bfbSMagnus Damm 	pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
52b8b47bfbSMagnus Damm 	pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
531da177e4SLinus Torvalds 
54b8b47bfbSMagnus Damm 	pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
55b8b47bfbSMagnus Damm 	pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
561da177e4SLinus Torvalds 
57e036eaa6SMagnus Damm 	mcr = ctrl_inl(SH7751_MCR);
581da177e4SLinus Torvalds 	mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
59b8b47bfbSMagnus Damm 	pci_write_reg(chan, mcr, SH4_PCIMCR);
601da177e4SLinus Torvalds 
61b8b47bfbSMagnus Damm 	pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
62b8b47bfbSMagnus Damm 	pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
63b8b47bfbSMagnus Damm 	pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
64b8b47bfbSMagnus Damm 	pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
65959f85f8SPaul Mundt 
661da177e4SLinus Torvalds 	return 0;
671da177e4SLinus Torvalds }
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