1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4/ { 5 compatible = "jcore,j2-soc"; 6 model = "J2 FPGA SoC on Mimas v2 board"; 7 8 #address-cells = <1>; 9 #size-cells = <1>; 10 11 interrupt-parent = <&aic>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "jcore,j2"; 20 reg = <0>; 21 clock-frequency = <50000000>; 22 d-cache-size = <8192>; 23 i-cache-size = <8192>; 24 d-cache-block-size = <16>; 25 i-cache-block-size = <16>; 26 }; 27 }; 28 29 memory@10000000 { 30 device_type = "memory"; 31 reg = <0x10000000 0x4000000>; 32 }; 33 34 aliases { 35 serial0 = &uart0; 36 spi0 = &spi0; 37 }; 38 39 chosen { 40 stdout-path = "serial0"; 41 }; 42 43 soc@abcd0000 { 44 compatible = "simple-bus"; 45 ranges = <0 0xabcd0000 0x100000>; 46 47 #address-cells = <1>; 48 #size-cells = <1>; 49 50 aic: interrupt-controller@200 { 51 compatible = "jcore,aic1"; 52 reg = <0x200 0x10>; 53 interrupt-controller; 54 #interrupt-cells = <1>; 55 }; 56 57 cache-controller@c0 { 58 compatible = "jcore,cache"; 59 reg = <0xc0 4>; 60 }; 61 62 timer@200 { 63 compatible = "jcore,pit"; 64 reg = <0x200 0x30>; 65 interrupts = <0x48>; 66 }; 67 68 spi0: spi@40 { 69 compatible = "jcore,spi2"; 70 71 #address-cells = <1>; 72 #size-cells = <0>; 73 74 spi-max-frequency = <25000000>; 75 76 reg = <0x40 0x8>; 77 78 sdcard@0 { 79 compatible = "mmc-spi-slot"; 80 reg = <0>; 81 spi-max-frequency = <25000000>; 82 voltage-ranges = <3200 3400>; 83 mode = <0>; 84 }; 85 }; 86 87 uart0: serial@100 { 88 clock-frequency = <125000000>; 89 compatible = "xlnx,xps-uartlite-1.00.a"; 90 current-speed = <19200>; 91 xlnx,use-parity = <0>; 92 xlnx,data-bits = <8>; 93 device_type = "serial"; 94 interrupts = <0x12>; 95 port-number = <0>; 96 reg = <0x100 0x10>; 97 }; 98 }; 99}; 100